A Synthesis System for Testable and Area-efficient Finite State Machines
Author : Chun-Yeh Liu
Publisher :
Page : 316 pages
File Size : 10,38 MB
Release : 1994
Category :
ISBN :
Author : Chun-Yeh Liu
Publisher :
Page : 316 pages
File Size : 10,38 MB
Release : 1994
Category :
ISBN :
Author : Tiziano Villa
Publisher : Springer Science & Business Media
Page : 382 pages
File Size : 30,16 MB
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 1461561558
Synthesis of Finite State Machines: Logic Optimization is the second in a set of two monographs devoted to the synthesis of Finite State Machines (FSMs). The first volume, Synthesis of Finite State Machines: Functional Optimization, addresses functional optimization, whereas this one addresses logic optimization. The result of functional optimization is a symbolic description of an FSM which represents a sequential function chosen from a collection of permissible candidates. Logic optimization is the body of techniques for converting a symbolic description of an FSM into a hardware implementation. The mapping of a given symbolic representation into a two-valued logic implementation is called state encoding (or state assignment) and it impacts heavily area, speed, testability and power consumption of the realized circuit. The first part of the book introduces the relevant background, presents results previously scattered in the literature on the computational complexity of encoding problems, and surveys in depth old and new approaches to encoding in logic synthesis. The second part of the book presents two main results about symbolic minimization; a new procedure to find minimal two-level symbolic covers, under face, dominance and disjunctive constraints, and a unified frame to check encodability of encoding constraints and find codes of minimum length that satisfy them. The third part of the book introduces generalized prime implicants (GPIs), which are the counterpart, in symbolic minimization of two-level logic, to prime implicants in two-valued two-level minimization. GPIs enable the design of an exact procedure for two-level symbolic minimization, based on a covering step which is complicated by the need to guarantee encodability of the final cover. A new efficient algorithm to verify encodability of a selected cover is presented. If a cover is not encodable, it is shown how to augment it minimally until an encodable superset of GPIs is determined. To handle encodability the authors have extended the frame to satisfy encoding constraints presented in the second part. The covering problems generated in the minimization of GPIs tend to be very large. Recently large covering problems have been attacked successfully by representing the covering table with binary decision diagrams (BDD). In the fourth part of the book the authors introduce such techniques and extend them to the case of the implicit minimization of GPIs, where the encodability and augmentation steps are also performed implicitly. Synthesis of Finite State Machines: Logic Optimization will be of interest to researchers and professional engineers who work in the area of computer-aided design of integrated circuits.
Author :
Publisher :
Page : 662 pages
File Size : 15,89 MB
Release : 1998
Category : Dissertations, Academic
ISBN :
Author :
Publisher : Institute of Electrical & Electronics Engineers(IEEE)
Page : 458 pages
File Size : 31,33 MB
Release : 2001
Category : Computers
ISBN : 9780769511221
Collects 58 papers from the April/May 2001 symposium that explore new approaches in the testing of electronic circuits and systems. Key areas in testing are discussed, such as BIST, analog measurement, fault tolerance, diagnosis methods, scan chain design, memory test and diagnosis, and test data compression and compaction. Also on the program are sessions on emerging areas that are gaining prominence, including low power testing, testing high speed circuits on low cost testers, processor based self test techniques, and core- based system-on-chip testing. Some of the topics are robust and low cost BIST architectures for sequential fault testing in datapath multipliers, a method for measuring the cycle-to-cycle period jitter of high-frequency clock signals, fault equivalence identification using redundancy information and static and dynamic extraction, and test scheduling for minimal energy consumption under power constraints. No subject index. c. Book News Inc.
Author : Alexander Barkalov
Publisher : Springer Science & Business Media
Page : 245 pages
File Size : 27,76 MB
Release : 2009-11-25
Category : Technology & Engineering
ISBN : 3642043097
This book presents the hardware implementation of control algorithms represented by graph-schemes of algorithm. It includes new methods of logic synthesis and optimization for logic circuits of Mealy and Moore FSMs oriented on both ASIC and FPLD.
Author :
Publisher :
Page : 464 pages
File Size : 24,30 MB
Release : 2001
Category : Application-specific integrated circuits
ISBN :
Author : Andreas Kuehlmann
Publisher : Springer Science & Business Media
Page : 699 pages
File Size : 44,42 MB
Release : 2012-12-06
Category : Computers
ISBN : 1461502926
In 2002, the International Conference on Computer Aided Design (ICCAD) celebrates its 20th anniversary. This book commemorates contributions made by ICCAD to the broad field of design automation during that time. The foundation of ICCAD in 1982 coincided with the growth of Large Scale Integration. The sharply increased functionality of board-level circuits led to a major demand for more powerful Electronic Design Automation (EDA) tools. At the same time, LSI grew quickly and advanced circuit integration became widely avail able. This, in turn, required new tools, using sophisticated modeling, analysis and optimization algorithms in order to manage the evermore complex design processes. Not surprisingly, during the same period, a number of start-up com panies began to commercialize EDA solutions, complementing various existing in-house efforts. The overall increased interest in Design Automation (DA) re quired a new forum for the emerging community of EDA professionals; one which would be focused on the publication of high-quality research results and provide a structure for the exchange of ideas on a broad scale. Many of the original ICCAD volunteers were also members of CANDE (Computer-Aided Network Design), a workshop of the IEEE Circuits and Sys tem Society. In fact, it was at a CANDE workshop that Bill McCalla suggested the creation of a conference for the EDA professional. (Bill later developed the name).
Author : Alexander Barkalov
Publisher : Springer Science & Business Media
Page : 283 pages
File Size : 36,21 MB
Release : 2008-07-17
Category : Technology & Engineering
ISBN : 3540692851
One of the very important parts of any digital system is the control unit, coordin- ing interplay of other system blocks. As a rule, control units have irregular str- ture, which makes process of their logic circuits design very sophisticated. In case of complex logic controllers, the problem of system design is reduced practically to the design of control units. Actually, we observe a real technical boom connected with achievements in semiconductor technology. One of these is the development of integrated circuit known as the "systems-on-a-programmable- chip" (SoPC), where the number of elements approaches one billion. Because of the extreme complexity of microchips, it is very important to develop effective design methods oriented on particular properties of logical elements. Solution of this problem permits impr- ing functional capabilities of the target digital system inside single SoPC chip. As majority of researches point out, design methods used in case of industrial packages are, in case of complex digital system design, far from optimal. Similar problems concern the design of control units with standard ?eld-programmable logic devices (FPLD), such as PLA, PAL, GAL, CPLD, and FPGA. Let us point out that modern SoPC are based on CPLD or FPGA technology. Thus, the development of eff- tive design methods oriented on FPLD implementation of logic circuits used in the control units still remains the problem of great importance.
Author :
Publisher :
Page : 268 pages
File Size : 21,94 MB
Release : 1990
Category : Aeronautics
ISBN :
Author : Alexander Barkalov
Publisher : Springer Nature
Page : 257 pages
File Size : 25,69 MB
Release : 2020-01-08
Category : Technology & Engineering
ISBN : 3030382958
This book focuses on control units, which are a vital part of modern digital systems, and responsible for the efficiency of controlled systems. The model of a finite state machine (FSM) is often used to represent the behavior of a control unit. As a rule, control units have irregular structures that make it impossible to design their logic circuits using the standard library cells. Design methods depend strongly on such factors as the FSM used, specific features of the logic elements implemented in the FSM logic circuit, and the characteristics of the control algorithm to be interpreted. This book discusses Moore and Mealy FSMs implemented with FPGA chips, including look-up table elements (LUT) and embedded memory blocks (EMB). It is crucial to minimize the number of LUTs and EMBs in an FSM logic circuit, as well as to make the interconnections between the logic elements more regular, and various methods of structural decompositions can be used to solve this problem. These methods are reduced to the presentation of an FSM circuit as a composition of different logic blocks, the majority of which implement systems of intermediate logic functions different (and much simpler) than input memory functions and FSM output functions. The structural decomposition results in multilevel FSM circuits having fewer logic elements than equivalent single-level circuits. The book describes well-known methods of structural decomposition and proposes new ones, examining their impact on the final amount of hardware in an FSM circuit. It is of interest to students and postgraduates in the area of Computer Science, as well as experts involved in designing digital systems with complex control units. The proposed models and design methods open new possibilities for creating logic circuits of control units with an optimal amount of hardware and regular interconnections.