Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip


Book Description

This book describes several techniques to address variation-related design challenges for analog blocks in mixed-signal systems-on-chip. The methods presented are results from recent research works involving receiver front-end circuits, baseband filter linearization, and data conversion. These circuit-level techniques are described, with their relationships to emerging system-level calibration approaches, to tune the performances of analog circuits with digital assistance or control. Coverage also includes a strategy to utilize on-chip temperature sensors to measure the signal power and linearity characteristics of analog/RF circuits, as demonstrated by test chip measurements. Describes a variety of variation-tolerant analog circuit design examples, including from RF front-ends, high-performance ADCs and baseband filters; Includes built-in testing techniques, linked to current industrial trends; Balances digitally-assisted performance tuning with analog performance tuning and mismatch reduction approaches; Describes theoretical concepts as well as experimental results for test chips designed with variation-aware techniques.




Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip


Book Description

This book describes several techniques to address variation-related design challenges for analog blocks in mixed-signal systems-on-chip. The methods presented are results from recent research works involving receiver front-end circuits, baseband filter linearization, and data conversion. These circuit-level techniques are described, with their relationships to emerging system-level calibration approaches, to tune the performances of analog circuits with digital assistance or control. Coverage also includes a strategy to utilize on-chip temperature sensors to measure the signal power and linearity characteristics of analog/RF circuits, as demonstrated by test chip measurements. Describes a variety of variation-tolerant analog circuit design examples, including from RF front-ends, high-performance ADCs and baseband filters; Includes built-in testing techniques, linked to current industrial trends; Balances digitally-assisted performance tuning with analog performance tuning and mismatch reduction approaches; Describes theoretical concepts as well as experimental results for test chips designed with variation-aware techniques.




Timing Performance of Nanometer Digital Circuits Under Process Variations


Book Description

This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level “design hints” are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.




Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design


Book Description

Improving the performance of existing technologies has always been a focal practice in the development of computational systems. However, as circuitry is becoming more complex, conventional techniques are becoming outdated and new research methodologies are being implemented by designers. Performance Optimization Techniques in Analog, Mix-Signal, and Radio-Frequency Circuit Design features recent advances in the engineering of integrated systems with prominence placed on methods for maximizing the functionality of these systems. This book emphasizes prospective trends in the field and is an essential reference source for researchers, practitioners, engineers, and technology designers interested in emerging research and techniques in the performance optimization of different circuit designs.




Technologies for Smart Sensors and Sensor Fusion


Book Description

Exciting new developments are enabling sensors to go beyond the realm of simple sensing of movement or capture of images to deliver information such as location in a built environment, the sense of touch, and the presence of chemicals. These sensors unlock the potential for smarter systems, allowing machines to interact with the world around them in more intelligent and sophisticated ways. Featuring contributions from authors working at the leading edge of sensor technology, Technologies for Smart Sensors and Sensor Fusion showcases the latest advancements in sensors with biotechnology, medical science, chemical detection, environmental monitoring, automotive, and industrial applications. This valuable reference describes the increasingly varied number of sensors that can be integrated into arrays, and examines the growing availability and computational power of communication devices that support the algorithms needed to reduce the raw sensor data from multiple sensors and convert it into the information needed by the sensor array to enable rapid transmission of the results to the required point. Using both SI and US units, the text: Provides a fundamental and analytical understanding of the underlying technology for smart sensors Discusses groundbreaking software and sensor systems as well as key issues surrounding sensor fusion Exemplifies the richness and diversity of development work in the world of smart sensors and sensor fusion Offering fresh insight into the sensors of the future, Technologies for Smart Sensors and Sensor Fusion not only exposes readers to trends but also inspires innovation in smart sensor and sensor system development.




VLSI Architecture for Signal, Speech, and Image Processing


Book Description

This new volume introduces various VLSI (very-large-scale integration) architecture for DSP filters, speech filters, and image filters, detailing their key applications and discussing different aspects and technologies used in VLSI design, models and architectures, and more. The volume explores the major challenges with the aim to develop real-time hardware architecture designs that are compact and accurate. It provides useful research in the field of computer arithmetic and can be applied for various arithmetic circuits, for their digital implementation schemes, and for performance considerations.




Cognitive Radio Oriented Wireless Networks


Book Description

This book constitutes the refereed proceedings of the 13th EAI International Conference on Cognitive Radio Oriented Wireless Networks, CROWNCOM 2018, held in Ghent, Belgium, in September 2018. The 20 revised full papers were selected from 26 submissions. The papers are organized thematically in tracks: Experimental, Licensed Shared Access and Dynamic Spectrum Access, and PHX and Sensing.




Practical Applications in Reliability Engineering


Book Description

This book compiles and examines advanced technologies in the field of reliability and risk analysis. It presents comprehensive methodologies and up-to-date software along with examples of practical case studies from industrial areas to provide a realistic and authentic platform for readers.




Nanoscale VLSI


Book Description

This book describes methodologies in the design of VLSI devices, circuits and their applications at nanoscale levels. The book begins with the discussion on the dominant role of power dissipation in highly scaled devices.The 15 Chapters of the book are classified under four sections that cover design, modeling, and simulation of electronic, magnetic and compound semiconductors for their applications in VLSI devices, circuits, and systems. This comprehensive volume eloquently presents the design methodologies for ultra–low power VLSI design, potential post–CMOS devices, and their applications from the architectural and system perspectives. The book shall serve as an invaluable reference book for the graduate students, Ph.D./ M.S./ M.Tech. Scholars, researchers, and practicing engineers working in the frontier areas of nanoscale VLSI design.




Stochastic Process Variation in Deep-Submicron CMOS


Book Description

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and necessary circuit realizations for on-chip monitoring and performance calibration. The associated problems are addressed at various abstraction levels, i.e. circuit level, architecture level and system level. It therefore provides a broad view on the various solutions that have to be used and their possible combination in very effective complementary techniques for both analog/mixed-signal and digital circuits. The feasibility of the described algorithms and built-in circuitry has been verified by measurements from the silicon prototypes fabricated in standard 90 nm and 65 nm CMOS technology.