Author : Hubert Kaeslin
Publisher : Cambridge University Press
Page : 878 pages
File Size : 47,79 MB
Release : 2008-04-28
Category : Technology & Engineering
ISBN : 0521882672
This practical, tool-independent guide to designing digital circuits takes a unique, top-down approach, reflecting the nature of the design process in industry. Starting with architecture design, the book comprehensively explains the why and how of digital circuit design, using the physics designers need to know, and no more.
Author : Durgesh Nandan
Publisher : CRC Press
Page : 342 pages
File Size : 32,65 MB
Release : 2022-11-03
Category : Computers
ISBN : 1000565106
This new volume introduces various VLSI (very-large-scale integration) architecture for DSP filters, speech filters, and image filters, detailing their key applications and discussing different aspects and technologies used in VLSI design, models and architectures, and more. The volume explores the major challenges with the aim to develop real-time hardware architecture designs that are compact and accurate. It provides useful research in the field of computer arithmetic and can be applied for various arithmetic circuits, for their digital implementation schemes, and for performance considerations.
Author : Xinmiao Zhang
Publisher : CRC Press
Page : 410 pages
File Size : 18,56 MB
Release : 2017-12-19
Category : Technology & Engineering
ISBN : 148222965X
Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI Architectures for Modern Error-Correcting Codes serves as a bridge connecting advancements in coding theory to practical hardware implementations. Instead of focusing on circuit-level design techniques, the book highlights integrated algorithmic and architectural transformations that lead to great improvements on throughput, silicon area requirement, and/or power consumption in the hardware implementation. The goal of this book is to provide a comprehensive and systematic review of available techniques and architectures, so that they can be easily followed by system and hardware designers to develop en/decoder implementations that meet error-correcting performance and cost requirements. This book can be also used as a reference for graduate-level courses on VLSI design and error-correcting coding. Particular emphases are placed on hard- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parity-check (LDPC) codes. These codes are among the best candidates for modern and emerging applications due to their good error-correcting performance and lower implementation complexity compared to other codes. To help explain the computations and en/decoder architectures, many examples and case studies are included. More importantly, discussions are provided on the advantages and drawbacks of different implementation approaches and architectures.
Author : Maurizio Martina
Publisher : Institution of Engineering and Technology
Page : 385 pages
File Size : 15,70 MB
Release : 2019-10-07
Category : Technology & Engineering
ISBN : 1785617109
This book addresses future video coding from the perspective of hardware implementation and architecture design, with particular focus on approximate computing and the energy-quality scalability paradigm. Challenges in deploying VLSI architectures for video coding are identified and potential solutions postulated with reference to recent research in the field. The book offers systematic coverage of the designs, techniques and paradigms that will most likely be exploited in the design of VLSI architectures for future video coding systems. Written by a team of expert authors from around the world, and brought together by an editor who is a recognised authority in the field, this book is a useful resource for academics and industry professionals working on VLSI implementation of video codecs.
Author : Peter M. Kuhn
Publisher : Springer Science & Business Media
Page : 242 pages
File Size : 43,13 MB
Release : 2013-06-29
Category : Computers
ISBN : 1475744749
MPEG-4 is the multimedia standard for combining interactivity, natural and synthetic digital video, audio and computer-graphics. Typical applications are: internet, video conferencing, mobile videophones, multimedia cooperative work, teleteaching and games. With MPEG-4 the next step from block-based video (ISO/IEC MPEG-1, MPEG-2, CCITT H.261, ITU-T H.263) to arbitrarily-shaped visual objects is taken. This significant step demands a new methodology for system analysis and design to meet the considerably higher flexibility of MPEG-4. Motion estimation is a central part of MPEG-1/2/4 and H.261/H.263 video compression standards and has attracted much attention in research and industry, for the following reasons: it is computationally the most demanding algorithm of a video encoder (about 60-80% of the total computation time), it has a high impact on the visual quality of a video encoder, and it is not standardized, thus being open to competition. Algorithms, Complexity Analysis, and VLSI Architectures for MPEG-4 Motion Estimation covers in detail every single step in the design of a MPEG-1/2/4 or H.261/H.263 compliant video encoder: Fast motion estimation algorithms Complexity analysis tools Detailed complexity analysis of a software implementation of MPEG-4 video Complexity and visual quality analysis of fast motion estimation algorithms within MPEG-4 Design space on motion estimation VLSI architectures Detailed VLSI design examples of (1) a high throughput and (2) a low-power MPEG-4 motion estimator. Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation is an important introduction to numerous algorithmic, architectural and system design aspects of the multimedia standard MPEG-4. As such, all researchers, students and practitioners working in image processing, video coding or system and VLSI design will find this book of interest.
Author : J. W. Dally
Publisher : Springer Science & Business Media
Page : 256 pages
File Size : 44,60 MB
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 1461319951
Concurrent data structures simplify the development of concurrent programs by encapsulating commonly used mechanisms for synchronization and commu nication into data structures. This thesis develops a notation for describing concurrent data structures, presents examples of concurrent data structures, and describes an architecture to support concurrent data structures. Concurrent Smalltalk (CST), a derivative of Smalltalk-80 with extensions for concurrency, is developed to describe concurrent data structures. CST allows the programmer to specify objects that are distributed over the nodes of a concurrent computer. These distributed objects have many constituent objects and thus can process many messages simultaneously. They are the foundation upon which concurrent data structures are built. The balanced cube is a concurrent data structure for ordered sets. The set is distributed by a balanced recursive partition that maps to the subcubes of a binary 7lrcube using a Gray code. A search algorithm, VW search, based on the distance properties of the Gray code, searches a balanced cube in O(log N) time. Because it does not have the root bottleneck that limits all tree-based data structures to 0(1) concurrency, the balanced cube achieves 0C.:N) con currency. Considering graphs as concurrent data structures, graph algorithms are pre sented for the shortest path problem, the max-flow problem, and graph parti tioning. These algorithms introduce new synchronization techniques to achieve better performance than existing algorithms.
Author : Leibo Liu
Publisher : Springer
Page : 348 pages
File Size : 38,71 MB
Release : 2019-02-20
Category : Computers
ISBN : 9811363625
This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error. After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method.
Author : Brian Randell
Publisher : Prentice Hall International (UK)
Page : 456 pages
File Size : 25,68 MB
Release : 1983
Category : Computers
ISBN :
Author : S.B. Furber
Publisher : Routledge
Page : 398 pages
File Size : 29,72 MB
Release : 2017-09-19
Category : Technology & Engineering
ISBN : 1351405373
With the expectation that architectural improvements will play a significant role inadvancing processor performance, it is critical for readers to maintain an up-to-date,unified overview of technological advances in this vital research area.Gathering into one place material that had been scattered throughout the literaturemakingit difficult to obtain detailed information on computer designs-this importantbook describes the main architectural and organizational features of modem mini- andmicrocomputers. In addition, it explains the RISC philosophy by supplying historicalbackground information and excellent examples of several commercially available RISCmicroprocessors.Limiting attention to VLSI implementations of RISC processors, VLSI RISCArchitecture and Organization offers insight into design issues that arose indeveloping a RISC system, using the VLSI RISC chip set developed at AcornComputers Limited as an example ... discusses options considered during the designprocess, the basis for the decisions made, and implementation details . . . describescontemporary RISC architecture, comparing and contrasting different designs ... andlooks at future trends in RISC research.Discussing the topic cohesively and comprehensively-from initial study into reducedinstructions sets to the widespread introduction of RISC architectures into mainstreamcomputer products-VLSI RISC Architecture and Organization is aninvaluable reference for electrical, electronics, and computer engineers; computerarchitects and scientists; hardware systems designers; and upper-level undergraduate andgraduate students in computer science and electrical engineering courses.
Author : Hubert Kaeslin
Publisher : Morgan Kaufmann
Page : 599 pages
File Size : 50,30 MB
Release : 2014-12-07
Category : Technology & Engineering
ISBN : 0128007729
Top-Down VLSI Design: From Architectures to Gate-Level Circuits and FPGAs represents a unique approach to learning digital design. Developed from more than 20 years teaching circuit design, Doctor Kaeslin’s approach follows the natural VLSI design flow and makes circuit design accessible for professionals with a background in systems engineering or digital signal processing. It begins with hardware architecture and promotes a system-level view, first considering the type of intended application and letting that guide your design choices. Doctor Kaeslin presents modern considerations for handling circuit complexity, throughput, and energy efficiency while preserving functionality. The book focuses on application-specific integrated circuits (ASICs), which along with FPGAs are increasingly used to develop products with applications in telecommunications, IT security, biomedical, automotive, and computer vision industries. Topics include field-programmable logic, algorithms, verification, modeling hardware, synchronous clocking, and more. Demonstrates a top-down approach to digital VLSI design. Provides a systematic overview of architecture optimization techniques. Features a chapter on field-programmable logic devices, their technologies and architectures. Includes checklists, hints, and warnings for various design situations. Emphasizes design flows that do not overlook important action items and which include alternative options when planning the development of microelectronic circuits.
