Aging Aware Timing Analysis of Digital Integrated Circuits for Varying Use Profiles
Author : Veit B. Kleeberger
Publisher :
Page : 40 pages
File Size : 26,24 MB
Release : 2012
Category :
ISBN :
Author : Veit B. Kleeberger
Publisher :
Page : 40 pages
File Size : 26,24 MB
Release : 2012
Category :
ISBN :
Author : Basel Halak
Publisher : Springer Nature
Page : 228 pages
File Size : 29,25 MB
Release : 2019-09-30
Category : Technology & Engineering
ISBN : 3030237818
This book provides comprehensive coverage of the latest research into integrated circuits’ ageing, explaining the causes of this phenomenon, describing its effects on electronic systems, and providing mitigation techniques to build ageing-resilient circuits.
Author : Suryanarayana Pendela
Publisher :
Page : 95 pages
File Size : 22,42 MB
Release : 2010
Category :
ISBN :
Much of the Semiconductor Industry's success can be attributed to Moore's law which states that the number of transistors on an integrated circuit would double approximately every two years. Semiconductor industry has ever since progressed from designs with a few hundred transistors to today's complex designs incorporating millions of transistors. The current era of nanometer technologies threatens to impact the sustainability of Moore's law with random variations in the manufacturing process impacting yield in a big way. Considerable research efforts have since been devoted to account for these variations leading to a new paradigm called Design for Manufacturing (DFM). Traditional Static Timing Analysis (STA) has given way to Statistical Static Timing Analysis (SSTA) techniques wherein the parameters considered are treated as random variables with assigned probability distribution functions. However, SSTA is still not seen as a mature flow for commercial adoption, owing to the inherent complex nature of the SSTA algorithms. In this thesis, we propose an alternate framework to STA under the presence of process variations using Interval Valued Static Timing Analysis (IVSTA). Process variations are accounted for by using a macro-modeling framework providing an efficient and fast timing analysis technique. Results on standard benchmarks show that IVSTA can predict the timing slack by a margin of 5-10% error and huge improvement of runtime compared to traditional corner based analysis. The framework involves a one-time characterization of the standard cell library and can be incorporated without much modification to the design flow. An iterative optimization framework using IVSTA engine is also presented which optimizes a routed netlist for variations at a minimum penalty of area and power.
Author : Dominik Lorenz
Publisher :
Page : 150 pages
File Size : 16,39 MB
Release : 2012
Category :
ISBN :
Author : Jiayong Le
Publisher :
Page : 0 pages
File Size : 24,25 MB
Release : 2006
Category :
ISBN :
Author : Saket Gupta
Publisher :
Page : 153 pages
File Size : 17,94 MB
Release : 2012
Category :
ISBN :
Author :
Publisher :
Page : pages
File Size : 18,52 MB
Release : 2015
Category :
ISBN :
Author : Khaled R. Heloue
Publisher :
Page : pages
File Size : 36,21 MB
Release : 2010
Category :
ISBN :
Author : Nico Hellwege
Publisher :
Page : pages
File Size : 33,70 MB
Release : 2015
Category :
ISBN :
Author : J. Bhasker
Publisher : Springer Science & Business Media
Page : 588 pages
File Size : 27,43 MB
Release : 2009-04-03
Category : Technology & Engineering
ISBN : 0387938206
iming, timing, timing! That is the main concern of a digital designer charged with designing a semiconductor chip. What is it, how is it T described, and how does one verify it? The design team of a large digital design may spend months architecting and iterating the design to achieve the required timing target. Besides functional verification, the t- ing closure is the major milestone which dictates when a chip can be - leased to the semiconductor foundry for fabrication. This book addresses the timing verification using static timing analysis for nanometer designs. The book has originated from many years of our working in the area of timing verification for complex nanometer designs. We have come across many design engineers trying to learn the background and various aspects of static timing analysis. Unfortunately, there is no book currently ava- able that can be used by a working engineer to get acquainted with the - tails of static timing analysis. The chip designers lack a central reference for information on timing, that covers the basics to the advanced timing veri- cation procedures and techniques.