Design Space Exploration and Resource Management of Multi/Many-Core Systems


Book Description

The increasing demand of processing a higher number of applications and related data on computing platforms has resulted in reliance on multi-/many-core chips as they facilitate parallel processing. However, there is a desire for these platforms to be energy-efficient and reliable, and they need to perform secure computations for the interest of the whole community. This book provides perspectives on the aforementioned aspects from leading researchers in terms of state-of-the-art contributions and upcoming trends.







High-Level Synthesis


Book Description

This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. It includes an overview of available EDA tool solutions and their applicability to design problems.







Design Space Exploration Using Heuristic Algorithms


Book Description

In the field of High Performance Computing, Field Programmable Gate Arrays are growing exponentially. The use of the High Level Synthesis Tools has resulted in an increase in the applications which are intensive in computation such as Cognitive Computing Artificial Intelligence due to the ease of its usage. The advantage of the increasing level of abstraction in hardware design is it provides various configurations which have unique properties like area, power, performance which can be generated automatically with no need to write the input descriptions again. All of this would not be possible with the traditional languages such as Verilog or VHDL. This thesis mainly focuses on the above mentioned topic which helps in finding the most optimum solutions for the Design Space Exploration with the implementation of the two Heuristic Algorithms such as the Genetic Algorithm and the Simulated Annealing. This work mainly focuses on the exploration of High level synthesis for the design space exploration and its automation using Qt creator. The Heuristic Algorithms for the Design Space Exploration was developed to obtain the optimum values of the area versus latency. This optimum value is obtained by inserting and varying various attribute knobs like loop unrolling, arrays etc. in the benchmarks. These attributes play a very important role in obtaining the optimum values which can be controlled and tuned with the help of the knobs which generate various configurations of the micro architecture. It is hence not a feasible option to perform a brute search or an exhaustive search on these values due to the large design space and also complex and large designs, as a result this gives rise to the need of heuristic algorithms. The Genetic Algorithm and Simulated Annealing Algorithms are hence explored for each benchmark to obtain an optimum solution if not the best possible solution for a given design space. The comparison of these three types of searches is done using quality metrics like the Average Distance to Reference Set (ADRS) and Dominance which shows that the Genetic Algorithm gives us a better result in comparison to Simulated Annealing. The whole process is automated using Qt Creator which generates a Graphical User Interface for the process of automation.