Book Description

With increasing complexity and size of VLSI systems, RTL can no longer be a viable design entry point. On the other hand, higher levels of abstraction takes the design description farther away from the physical characteristics of the system, making valuable, and necessary information unavailable to the synthesis process leading to problems in achieving design convergence. This work addresses three significant problems in providing a direct link to circuit and physical synthesis during high level design space exploration. (1) Developing methodologies for coupling circuit synthesis with high level synthesis design-space exploration for the design of high performance DSP designs, (2) Developing algorithms to couple high level synthesis with physical synthesis by performing incremental placement during high level synthesis design-space exploration, (3) Developing algorithms to couple high level synthesis and physical synthesis for vertically integrated 3D systems by performing simultaneous scheduling, binding and layer assignment for resources; and finding the best possible methodology for the performance optimization in terms of interconnect lengths in the critical path and inter-layer vias. Unlike previous research efforts that concentrate on obtaining estimates, our work aims at directly coupling high level synthesis decisions with circuit and layout synthesis. The proposed approaches allow us to examine larger design spaces to synthesize better designs, which would otherwise be pruned by a top-down synthesis flow. To leverage circuit level optimizations during high level design space exploration, we propose a methodology for performing on-demand resource topology modification using partial evaluation for constant operands during synthesis of application specific DSP circuits. We also propose a methodology to perform on-demand resizing of resources for the generation of constraint satisfying RTL at the end of behavioral synthesis. In order to integrate physical synthesis during high level exploration, we propose a methodology to perform incremental global placement in a high level synthesis framework. The high level exploration system uses a delay budget driven incremental placement engine for the generation of constraint satisfying placed RTL structures. We also demonstrate the application of the placement methodology to account for resource resizing that changes resource dimensions impacting the physical RTL structure and associated interconnect characteristics. We extend the scope of our work to address behavioral synthesis for vertically integrated three-dimensional systems and propose a methodology to perform physical-aware synthesis for these systems. The emergence of three-dimensional systems has provided novel avenues for miniaturization; delay and power minimization. We propose a methodology to perform simultaneous scheduling, binding and layer assignment for vertically integrated three dimensional systems. By choosing judicious cost functions, both the inter-layer vias and the total length of interconnects in the critical path can be minimized. We analyze the advantages these systems offer and how they can be leveraged during synthesis to obtain the best trade-off between minimization of inter-layer vias and the total length of interconnects in the critical path.