Book Description

Recently, three-dimensional (3D) integration technology has enabled researchers to explore novel architectures. Due to the growing memory requirements of modern signal processing applications, it was thought that digital signal processors (DSPs) could benefit from 3D memory integration technology where high-density memories are placed below processing cores. Until recently, it was believed that this integration could lower memory latencies by 45% to 60%, which would improve performance. 3D memory integration technology also allowed a large increase in the main memory bus width by using small through silicon vias (TSVs) instead of off-chip metal wires. This increase in the bus width meant each main memory request could bring more data into the last-level on-chip memory and improve the performance of streaming applications whose memory access behavior exhibits a large amount of spatial locality. My dissertation provides a more accurate 3D main memory model that demonstrates that the latency reduction of going from conventional DDR2 DRAM to 3D memory technology is roughly 4% instead of the often quoted 45% to 60%. With this model, I re-evaluate the performance impact of 3D main memory on DSPs and find the benefits from the latency savings are small. I next analyze current 3D main memory with Wide I/O, which can lower main memory latencies by 15.9% and greatly increase the main memory bus width. I demonstrate that using 3D main memory with Wide I/O and increasing the main memory bus width from 64 bits to 4,096 bits can improve the average performance of signal processing applications by 9.7%, but also increases average energy consumption by 2.6%. For energy-constraint DSPs that are often found in mobile devices, this increase may be unacceptable. To mitigate this energy increase, I propose novel techniques to dynamically scale the main memory bus width of a DSP based on the program phases of an application. These bandwidth scaling algorithms increase the main memory bus width during memory intense phases to improve performance and lower the bus width during compute intensive phases to improve energy efficiency. These algorithms can improve average DSP performance by 6.6% while increasing average energy consumption by only 0.5%.