Ageing of Integrated Circuits


Book Description

This book provides comprehensive coverage of the latest research into integrated circuits’ ageing, explaining the causes of this phenomenon, describing its effects on electronic systems, and providing mitigation techniques to build ageing-resilient circuits.










Lifetime Reliability-aware Design of Integrated Circuits


Book Description

This book covers the state-of-the-art research in design of modern electronic systems used in safety-critical applications such as medical devices, aircraft flight control, and automotive systems. The authors discuss lifetime reliability of digital systems, as well as an overview of the latest research in the field of reliability-aware design of integrated circuits. They address modeling approaches and techniques for evaluation and improvement of lifetime reliability for nano-scale CMOS digital circuits, as well as design algorithms that are the cornerstone of Computer Aided Design (CAD) of reliable VLSI circuits. In addition to developing lifetime reliability analysis and techniques for clocked storage elements (such as flip-flops), the authors also describe analysis and improvement strategies targeting commercial digital circuits.




Analog IC Reliability in Nanometer CMOS


Book Description

This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed. The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.







On Ageing Effects in Analogue Integrated Circuits


Book Description

The behaviour of electronic circuits is influenced by ageing effects. Modelling the behaviour of circuits is a standard approach for the design of faster, smaller, more reliable and more robust systems. In this thesis, we propose a formalization of robustness that is derived from a failure model, which is based purely on the behavioural specification of a system. For a given specification, simulation can reveal if a system does not comply with a specification, and thus provide a failure model. Ageing usually works against the specified properties, and ageing models can be incorporated to quantify the impact on specification violations, failures and robustness. We study ageing effects in the context of analogue circuits. Here, models must factor in infinitely many circuit states. Ageing effects have a cause and an impact that require models. On both these ends, the circuit state is highly relevant, an must be factored in. For example, static empirical models for ageing effects are not valid in many cases, because the assumed operating states do not agree with the circuit simulation results. ...










An Examination of CMOS Aging in Integrated Circuits and Novel Aging Detection Techniques for SRAM Cells


Book Description

This thesis work examines the problem of CMOS aging in VLSI integrated circuits. In nanoscale technologies, Negative and Positive Bias Temperature Instability causes an increase over time in the absolute value of the threshold voltage of PMOS and NMOS transistors which results in degraded circuit performance. Current methods to detect and compensate for aging in both digital and combinational logic and memory arrays are presented in this work. My own research contribution in the field of SRAM aging detection is then described. Modifications to standard 6T SRAM cells create a built in sensor which can detect effects of Bias Temperature Instability on the NMOS and PMOS transistors of an SRAM cell. The proposed design allows for a check process, which can observe an increase in transistor threshold voltage as a result of aging effects directly in a cell which is actually used as a memory unit. The proposed modifications allow for detections of aging while having a minimized impact on area and performance of a standard 6T SRAM cell.