An Examination of CMOS Aging in Integrated Circuits and Novel Aging Detection Techniques for SRAM Cells


Book Description

This thesis work examines the problem of CMOS aging in VLSI integrated circuits. In nanoscale technologies, Negative and Positive Bias Temperature Instability causes an increase over time in the absolute value of the threshold voltage of PMOS and NMOS transistors which results in degraded circuit performance. Current methods to detect and compensate for aging in both digital and combinational logic and memory arrays are presented in this work. My own research contribution in the field of SRAM aging detection is then described. Modifications to standard 6T SRAM cells create a built in sensor which can detect effects of Bias Temperature Instability on the NMOS and PMOS transistors of an SRAM cell. The proposed design allows for a check process, which can observe an increase in transistor threshold voltage as a result of aging effects directly in a cell which is actually used as a memory unit. The proposed modifications allow for detections of aging while having a minimized impact on area and performance of a standard 6T SRAM cell.




CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies


Book Description

The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.




Ageing of Integrated Circuits


Book Description

This book provides comprehensive coverage of the latest research into integrated circuits’ ageing, explaining the causes of this phenomenon, describing its effects on electronic systems, and providing mitigation techniques to build ageing-resilient circuits.




Low Power and Reliable SRAM Memory Cell and Array Design


Book Description

Success in the development of recent advanced semiconductor device technologies is due to the success of SRAM memory cells. This book addresses various issues for designing SRAM memory cells for advanced CMOS technology. To study LSI design, SRAM cell design is the best materials subject because issues about variability, leakage and reliability have to be taken into account for the design.




Analog IC Reliability in Nanometer CMOS


Book Description

This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed. The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.







Aging Degradation and Countermeasures


Book Description

This book summarizes the outcome of investigations on the effects of aging mechanisms induced parameter shifts and performance degradation in analog and mixed signal integrated circuits. Degradation induced due to aging mechanisms like bias temperature instability, conducting and non-conducting hot carrier injection in NMOS and PMOS devices leads to increased challenges in design of reliable circuits in deep-submicrometer CMOS technologies. The lifetime degradation induces threshold voltage and drain current shifts that can result into mismatch in matched transistor pairs which is especially important for analog and mixed signal circuit's accuracy. The investigations are done based on analytical evaluation, aging simulation and measurements using sample circuits implemented in state-of-the-art 32nm high-k metal gate CMOS technology. Calibration and correction techniques suitable for overcoming time varying aging induced circuit performance degradation are proposed and investigated. This book is structured to guide the reader from important aging mechanisms, over to aging degradation in analog and mixed signal building blocks and countermeasures to overcome these effects.




CMOS Test and Evaluation


Book Description




Robust SRAM Designs and Analysis


Book Description

This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design. Provides a complete and concise introduction to SRAM bitcell design and analysis; Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis; Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices; Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.




Radiation Hardened CMOS Integrated Circuits for Time-Based Signal Processing


Book Description

This book presents state-of-the-art techniques for radiation hardened high-resolution Time-to-Digital converters and low noise frequency synthesizers. Throughout the book, advanced degradation mechanisms and error sources are discussed and several ways to prevent such errors are presented. An overview of the prerequisite physics of nuclear interactions is given that has been compiled in an easy to understand chapter. The book is structured in a way that different hardening techniques and solutions are supported by theory and experimental data with their various tradeoffs. Based on leading-edge research, conducted in collaboration between KU Leuven and CERN, the European Center for Nuclear Research Describes in detail advanced techniques to harden circuits against ionizing radiation Provides a practical way to learn and understand radiation effects in time-based circuits Includes an introduction to the underlying physics, circuit design, and advanced techniques accompanied with experimental data