Clock Synchronization in Multiprocessor Systems
Author : Gokuldas K. Hegde
Publisher :
Page : 110 pages
File Size : 31,11 MB
Release : 1993
Category : Multiprocessors
ISBN :
Author : Gokuldas K. Hegde
Publisher :
Page : 110 pages
File Size : 31,11 MB
Release : 1993
Category : Multiprocessors
ISBN :
Author : Xida Li
Publisher :
Page : 116 pages
File Size : 15,95 MB
Release : 1997
Category : Multiprocessors
ISBN :
Author : Deog-Kyoon Jeong
Publisher :
Page : 304 pages
File Size : 37,87 MB
Release : 1989
Category : Integrated circuits
ISBN :
Microprocessors based on RISC (Reduced Instruction Set Computer) concepts have demonstrated an ability to provide more computing power at a given level of integration than conventional microprocessors. The next step is multiprocessors is critic al in achieving efficient hardware utilization. This thesis focuses on the communication capability of VLSI circuits and presents new circuit techniques as a guide to build an interconnection network of VLSI microprocessors. Two of the most prominent problems in a synchronous system, which most of the current computer systems are based on, have been clock skew and synchronization failure. A new concept called self-timed systems solves such problems but has not been accepted i n microprocessor implementations yet because of its complex design procedure and increased overhead. With this in mind, this thesis concentrated on a system in which individual synchronous subsystems are connected asynchronously. Synchronous subsystems op erate with a better control over clock skew using a phase locked loop (PLL) technique. Communication among subsystems is done asynchronously with a controlled synchronization failure rate. One advantage is that conventional VLSI design methodologies which are more efficient can still be applied. Circuit techniques for PLL-based clock generation are described along with stability criteria. The main objective of the circuit is to realize a zero delay buffer. Experimental results show the feasability of such circuits in VLSI. Synchronizer circuit co nfigurations in both bipolar and MOS technology that best utilize each device, or overcome the technology limit using a bandwidth doubling technique are shown. Interface techniques including handshake mechanisms in such a system are also described. These techniques are applied in designing a memory management unit and cache controller (MMU/CC) for a multiprocessor workstation, SPUR. A SPUR workstation is an example of synchronous subsystems cluster with independent clock frequency. The interface and communication aspect of the overall system are revealed through the description of the MMU/CC. The VLSI chip is implemented in 1.6 um CMOS technology with 68,000 transistors.
Author : Shiu-Ming Kam
Publisher :
Page : 84 pages
File Size : 13,30 MB
Release : 1989
Category :
ISBN :
Author : David L. Mills
Publisher : CRC Press
Page : 598 pages
File Size : 45,10 MB
Release : 2017-12-19
Category : Computers
ISBN : 1351834045
Carefully coordinated, reliable, and accurate time synchronization is vital to a wide spectrum of fields—from air and ground traffic control, to buying and selling goods and services, to TV network programming. Ill-gotten time could even lead to the unimaginable and cause DNS caches to expire, leaving the entire Internet to implode on the root servers. Written by the original developer of the Network Time Protocol (NTP), Computer Network Time Synchronization: The Network Time Protocol on Earth and in Space, Second Edition addresses the technological infrastructure of time dissemination, distribution, and synchronization—specifically the architecture, protocols, and algorithms of the NTP. This system has been active in one form or another for almost three decades on the Internet and numerous private networks on the nether side of firewalls. Just about everything today that can be connected to a network wire has support for NTP. This book: Describes the principal components of an NTP client and how it works with redundant servers and diverse network paths Provides an in-depth description of cryptographic and other critical algorithms Presents an overview of the engineering principles guiding network configuration Evaluating historic events that have taken place since computer network timekeeping started almost three decades ago, the author details a number of systems and drivers for current radio, satellites, and telephone modem dissemination and explains how we reckon the time, according to the stars and atoms. The original 16 chapters of the first edition have been rewritten, updated, and enhanced with new material. Four new chapters cover new algorithms and previously uncovered concepts, including timekeeping in space missions. Praise for the first edition: "... For those that need an exhaustive tome on all of the minutiae related to NTP and synchronization, this is the source. ... definitive ... this book should be considered the last word on the topic." —Ben Rothke on Slashdot.org "... the bible of the subject... contains enough information to take you just as far as you want to go....Dr. Mills is the original developer of NTP." —Books On-Line
Author : Hugh L. Brunk
Publisher :
Page : 162 pages
File Size : 19,49 MB
Release : 1990
Category :
ISBN :
Author : Ahmed Jerraya
Publisher : Morgan Kaufmann
Page : 604 pages
File Size : 25,93 MB
Release : 2005
Category : Computers
ISBN : 012385251X
Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications
Author : Sundararajan Sriram
Publisher : CRC Press
Page : 380 pages
File Size : 10,36 MB
Release : 2018-10-03
Category : Computers
ISBN : 1420048023
Techniques for Optimizing Multiprocessor Implementations of Signal Processing Applications An indispensable component of the information age, signal processing is embedded in a variety of consumer devices, including cell phones and digital television, as well as in communication infrastructure, such as media servers and cellular base stations. Multiple programmable processors, along with custom hardware running in parallel, are needed to achieve the computation throughput required of such applications. Reviews important research in key areas related to the multiprocessor implementation of multimedia systems Embedded Multiprocessors: Scheduling and Synchronization, Second Edition presents architectures and design methodologies for parallel systems in embedded digital signal processing (DSP) applications. It discusses application modeling techniques for multimedia systems, the incorporation of interprocessor communication costs into multiprocessor scheduling decisions, and a modeling methodology (the synchronization graph) for multiprocessor system performance analysis. The book also applies the synchronization graph model to develop hardware and software optimizations that can significantly reduce the interprocessor communication overhead of a given schedule. Chronicles recent activity dealing with single-chip multiprocessors and dataflow models This edition updates the background material on existing embedded multiprocessors, including single-chip multiprocessors. It also summarizes the new research on dataflow models for signal processing that has been carried out since the publication of the first edition. Harness the power of multiprocessors This book explores the optimization of interprocessor communication and synchronization in embedded multiprocessor systems. It shows you how to design multiprocessor computer systems that are streamlined for multimedia applications.
Author : Harald Bachner
Publisher : GRIN Verlag
Page : 73 pages
File Size : 17,29 MB
Release : 2007-07-26
Category : Computers
ISBN : 3638673669
Bachelor Thesis from the year 2007 in the subject Computer Science - Technical Computer Science, grade: 1,0, University of Applied Sciences Technikum Vienna (Informations- und Kommunikationssysteme), 29 entries in the bibliography, language: English, abstract: Clock synchronization is a necessary and critical part in most distributed systems. For many years NTP was the state-of-the-art way of synchronizing computer clocks distributed in space. However, as recent advances in miniaturization lead to the construction of smaller, more powerful and less power consuming computers, embedded devices, sensors and actuators, the need for more precise time synchronization grew. This work thus sets out to compare selected approaches to clock synchronization in distributed systems. The well known Global Positioning System is disseminating accurate time and frequency information from the International Institutes that keep the time, NTP can still do the same, but at different levels of accuracy as well as cost. Clock synchronization protocols like IEEE1588 or TTP and bus architectures like FlexRay evolved from the need to further propagate the timing information within small networks and therefore staying within the specified limits of preciseness.
Author : Marios Mavronicolas
Publisher : Springer Science & Business Media
Page : 356 pages
File Size : 16,97 MB
Release : 1997-09-10
Category : Computers
ISBN : 9783540635758
This book constitutes the refereed proceedings of the 11th International Workshop on Distributed Algorithms, WDAG '97, held in Saarbrücken, Germany, in September 1997. The volume presents 20 revised full papers selected from 59 submissions. Also included are three invited papers by leading researchers. The papers address a variety of current issues in the area of distributed algorithms and, more generally, distributed systems such as various particular algorithms, randomized computing, routing, networking, load balancing, scheduling, message-passing, shared-memory systems, communication, graph algorithms, etc.