Book Description

Abstract: Chaos is an interesting phenomenon for nonlinear systems that emerges due to its complex and unpredictable behavior. With the escalated use of low-powered edged-compute devices, data security at edge develops the need for security in communication. The fact that Chaos synchronizes over time for two different chaotic systems with their own unique initial conditions, is the base for chaos implementation in communication. This thesis talks about an encryption architecture suitable for on-chip integration with sensors. This concept provides a POC (proof of concept) that security is encrypted on the same chip with sensors itself. This algorithm is based on Chua’s chaotic system and implemented as Time Scaling Chaotic Shift Keying (TS-CSK). This POC research focuses on different chaotic equations that can be analyzed for encryption. In communication, encryption is being used with the help of microcontrollers or software implementations, which turn up using more power and complex hardware implementation. The small Internet of Things (IoT) devices are expected to be operated on low power and constrained with size. At the same time, these devices are highly vulnerable to security threats, which elevates the need to have low power/size hardware-based security. Since the discovery of chaotic equations, there have been various encryption applications with them. The goal of this research is to take the chaotic implementation to the CMOS level with the sensors on the same chip. This paper focuses on four different chaotic equations and achieves the simulations to find alternative architecture that can further reduce the power and the area. The spice simulation is demonstrated for the complete encryption/decryption architecture with Chua’s chaotic equation. The FPGA implementation is carried out to measure the hardware utilization of previously implemented Lorenz and Chua. The LUT (Look-Up Table) utilization is considered as merit to identify the resource utilization on the FPGA board with the help of the Xilinx System Generation toolbox. To advance the research with the goal of fabricating the circuit with CMOS, the cadence implementation of Chua has been achieved.