Author : Davide Brandano
Publisher :
Page : 272 pages
File Size : 19,66 MB
Release : 2012
Category :
ISBN :
Author : Feng Zhao
Publisher : Springer
Page : 106 pages
File Size : 17,15 MB
Release : 2014-11-25
Category : Technology & Engineering
ISBN : 3319122002
This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.
Author : George Gal
Publisher :
Page : pages
File Size : 48,89 MB
Release : 2013
Category :
ISBN :
"High-frequency fractional-N PLLs in CMOS technology in the 30 to 40 GHz are very dicult to design when considering power, area, phase noise requirements and frequency range of operation. One of the diculties is to synthesize the loop lter of the PLL such that it meets the phase noise characteristics using the information available for all the components that make up the PLL. At the same time, predicting the phase noise output of the PLL using extracted layout results takes a long time to simulate and often the solution does not converge, thereby lengthening the design cycle. This thesis proposes a new methodology for designing high performance wide-band fractional-N PLLs in the 30-40 GHz range. The method begins by rst designing the phase-frequency detector/charge-pump, voltage-controlled oscillator and frequency divider circuit for realization in a specic CMOS technology. The method of choice mixes insight deemed from both a theoretical and simulation perspective. Next, the loop lter is derived based on the layout extracted behaviour of each component. Once complete, all components of the PLL are described using the high-level description language of Verilog-A available in the Cadence tool set over its full range of operating characteristics. Ideally, these components would be fabricated rst and characterized afterward. The Verilog-A description of the PLL enables a fast and ecient simulation of the complete PLL in a closed-loop conguration. This latter steps allows further optimization of the overall design. Two chips have been fabricated; one in a 0.13 m CMOS process from IBM and another in a 65 nm CMOS process from TSMC. One chip contain the design of a 28 GHz VCO and another containing the design of a programmable frequency divider circuit. Experimental results for both chip are provided." --
Author : Behzad Razavi
Publisher : Cambridge University Press
Page : 509 pages
File Size : 44,8 MB
Release : 2020-01-30
Category : Technology & Engineering
ISBN : 1108494544
This modern, pedagogic textbook from leading author Behzad Razavi provides a comprehensive and rigorous introduction to CMOS PLL design, featuring intuitive presentation of theoretical concepts, extensive circuit simulations, over 200 worked examples, and 250 end-of-chapter problems. The perfect text for senior undergraduate and graduate students.
Author : Masoud Babaie
Publisher : River Publishers Circuits and
Page : 0 pages
File Size : 30,14 MB
Release : 2019
Category : Technology & Engineering
ISBN : 9788793609495
The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable.
Author : Yikun Yu
Publisher : Springer Science & Business Media
Page : 123 pages
File Size : 21,53 MB
Release : 2011-01-06
Category : Technology & Engineering
ISBN : 9400706626
Integrated 60GHz RF Beamforming in CMOS describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters with other key building blocks such as low noise amplifiers and power amplifiers are described in detail. Finally, this book describes the integration of a 60GHz CMOS amplifier and an antenna in a printed circuit-board (PCB) package.
Author : Kai Zhu
Publisher :
Page : 121 pages
File Size : 15,37 MB
Release : 2012
Category :
ISBN :
There has been a dramatic increase in wireless awareness among the user community in the past few years. As the wireless communication devices require more integration in terms of both hardware and software, the low-power integrated circuit (IC) solution has gained higher dedication and will dominate in the future radio-frequency IC (RFIC) design. Complementary Metal-Oxide Semiconductor (CMOS) process is extremely attractive for such applications because of its low cost and the possibility to integrate baseband and high frequency circuits on the same chip. The transceiver is often the most power-hungry block in a wireless communication system. The frequency divider (prescaler) and the voltage controlled oscillator (VCO) which are essential building blocks of in the frequency synthesizer of the transmitter are among the major sources of power consumption. This work focuses on prescalers. The injection-locked frequency dividers (ILFD) were introduced in the recent past for low-power frequency division. ILFDs can consume an order of magnitude lower power when compared to conventional flip-flop based dividers. However their range of operating frequency, also known as the locking range, is limited. ILFDs can be classified as LC tank, ring or relaxation oscillator based. There have been a lot of published works on the LC tank and ring oscillator based ILFDs. However, the one on relaxation oscillator based ILFD has been rarely reported, especially for RF applications. Besides, it is usually employed to implement a single division ratio such as 2, 3, 4 with an ILFD, while dual- or multi-moduli prescaler is more attractive to an RF synthesizer and are also rarely studied among published ILFDs. The goal of this work is to initially characterize the relaxation ILFD for RF applications. The locking range is optimized by the proposed topology. Besides, mathematical derivation is developed to verify the optimization. ILFD is also designed for different moduli with an easily controlled manner. Finally, the dual-modulus ILFD is also implemented based on the proposed structure. A prototype is fabricated in a 90-nm CMOS process and successfully tested.
Author : Venceslav F. Kroupa
Publisher : John Wiley & Sons
Page : 344 pages
File Size : 12,86 MB
Release : 2003-06-02
Category : Technology & Engineering
ISBN : 9780470848661
Phase lock loop frequency synthesis finds uses in a myriad of wireless applications - from local oscillators for receivers and transmitters to high performance RF test equipment. As the security and reliability of mobile communication transmissions have gained importance, PLL and frequency synthesisers have become increasingly topical subjects. Phase Lock Loops & Frequency Synthesis examines the various components that make up the phase lock loop design, including oscillators (crystal, voltage controlled), dividers and phase detectors. Interaction amongst the various components are also discussed. Real world problems such as power supply noise, shielding, grounding and isolation are given comprehensive coverage and solved examples with MATHCAD programs are presented throughout. * Presents a comprehesive study of phase lock loops and frequency synthesis in communication systems * Written by an internationally-recognised expert in the field * Details the problem of spurious signals in PLL frequency synthesizers, a topic neglected by available competing titles * Provides detailed theorectical background coupled with practical examples of state-of-the-art device design * MATHCAD programs and simulation software to accompany the design exercises and examples This combination of thorough theoretical treatment and guidance on practical applications will appeal to mobile communication circuit designers and advanced electrical engineering students.
Author : Robert Bogdan Staszewski
Publisher : John Wiley & Sons
Page : 281 pages
File Size : 32,57 MB
Release : 2006-09-22
Category : Technology & Engineering
ISBN : 0470041943
A new and innovative paradigm for RF frequency synthesis and wireless transmitter design Learn the techniques for designing and implementing an all-digital RF frequency synthesizer. In contrast to traditional RF techniques, this innovative book sets forth digitally intensive design techniques that lead the way to the development of low-cost, low-power, and highly integrated circuits for RF functions in deep submicron CMOS processes. Furthermore, the authors demonstrate how the architecture enables readers to integrate an RF front-end with the digital back-end onto a single silicon die using standard ASIC design flow. Taking a bottom-up approach that progressively builds skills and knowledge, the book begins with an introduction to basic concepts of frequency synthesis and then guides the reader through an all-digital RF frequency synthesizer design: Chapter 2 presents a digitally controlled oscillator (DCO), which is the foundation of a novel architecture, and introduces a time-domain model used for analysis and VHDL simulation Chapter 3 adds a hierarchical layer of arithmetic abstraction to the DCO that makes it easier to operate algorithmically Chapter 4 builds a phase correction mechanism around the DCO such that the system's frequency drift or wander performance matches that of the stable external frequency reference Chapter 5 presents an application of the all-digital RF synthesizer Chapter 6 describes the behavioral modeling and simulation methodology used in design The final chapter presents the implementation of a full transmitter and experimental results. The novel ideas presented here have been implemented and proven in two high-volume, commercial single-chip radios developed at Texas Instruments: Bluetooth and GSM. While the focus of the book is on RF frequency synthesizer design, the techniques can be applied to the design of other digitally assisted analog circuits as well. This book is a must-read for students and engineers who want to learn a new paradigm for RF frequency synthesis and wireless transmitter design using digitally intensive design techniques.
Author : Howard M. Berlin
Publisher : Prentice Hall
Page : 262 pages
File Size : 36,47 MB
Release : 1978
Category : Technology & Engineering
ISBN :
