Ultra-Low-Power Super Regenerative Receivers for Wireless Communication


Book Description

In this Thesis, both low frequency and high frequency ultra-low-power super-regenerative receiver with detailed circuits and system design for wireless communication networks has been proposed in this thesis. The SRR design has been applied super-regeneration theory which simplifies the receiver circuits implementation without increasing the power consumption and improves sensitivity. LC-SRO based energy detector, phase-locked loop, frequency locked loop, (PLL, FLL etc), Automatic -Gm controller, high speed, high conversion gain envelope detector (ED) and advanced quenching techniques (OQW, CQW) are presented in this thesis. This thesis also focuses on how to improve SRR's sensitivity (including SNR, BER) under high data rate with minimum power consumption. A series of advanced quenching techniques (OQW, CQW) are presented and studied for LC-VCO based SRO. High speed and high conversion gain envelope detector with automatic -gm controller will help the proposed SRR achieves great immunity to PVT variations and improve the data rate. Finally, FLL based frequency calibration techniques allows the SRR improves its sensitivity and selectivity against PVT variations.




Design and Simulation of 16 PSK Super Regenerative Receiver


Book Description

Abstract: Radio Frequency (RF) communication has developed tremendously over the past two decades. Short-range wireless applications, such as sensor networks, robotics, and home automation, require small area and low power consumption. The receiver must be designed in such a way that it optimizes the area with simple circuitry and minimizes its turn on time to achieve these requirements. This project focuses on designing the 16-PSK (Phase Shift Keying) super regenerative receiver to achieve digital transmission at a higher data rate with low power consumption. The receiver is designed with a Low Noise Amplifier (LNA), Super Regenerative Oscillator (SRO), buffers, RC networks, latches, and flip-flops. The receiver is designed at the 400 MHz frequency with 130nm Complementary Metal Oxide Semiconductor (CMOS) process technology. This receiver can correctly detect the -80 dBm, 4-Mbps signal with a power consumption of 164 [mu]W and Energy Per Bit (EPB) of 0.041nj/b.




Low-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits


Book Description

This unique book provides an overview of the current state of the art and very recent research results that have been achieved as part of the Low-Power Initiative of the European Union, in the field of analogue, RF and mixed-signal design methodologies and CAD tools.




Design of Ultra-Low Power Impulse Radios


Book Description

This book covers the fundamental principles behind the design of ultra-low power radios and how they can form networks to facilitate a variety of applications within healthcare and environmental monitoring, since they may operate for years off a small battery or even harvest energy from the environment. These radios are distinct from conventional radios in that they must operate with very constrained resources and low overhead. This book provides a thorough discussion of the challenges associated with designing radios with such constrained resources, as well as fundamental design concepts and practical approaches to implementing working designs. Coverage includes integrated circuit design, timing and control considerations, fundamental theory behind low power and time domain operation, and network/communication protocol considerations.




Architectures and Synthesizers for Ultra-low Power Fast Frequency-Hopping WSN Radios


Book Description

Wireless sensor networks have the potential to become the third wireless revolution after wireless voice networks in the 80s and wireless data networks in the late 90s. Unfortunately, radio power consumption is still a major bottleneck to the wide adoption of this technology. Different directions have been explored to minimize the radio consumption, but the major drawback of the proposed solutions is a reduced wireless link robustness. The primary goal of Architectures and Synthesizers for Ultra-low Power Fast Frequency-Hopping WSN Radios is to discuss, in detail, existing and new architectural and circuit level solutions for ultra-low power, robust, uni-directional and bi-directional radio links. Architectures and Synthesizers for Ultra-low Power Fast Frequency-Hopping WSN Radios guides the reader through the many system, circuit and technology trade-offs he will be facing in the design of communication systems for wireless sensor networks. Finally, this book, through different examples realized in both advanced CMOS and bipolar technologies opens a new path in the radio design, showing how radio link robustness can be guaranteed by techniques that were previously exclusively used in radio systems for middle or high end applications like Bluetooth and military communications while still minimizing the overall system power consumption.




The Design and Implementation of Low-Power CMOS Radio Receivers


Book Description

It is hardly a profound observation to note that we remain in the midst of a wireless revolution. In 1998 alone, over 150 million cell phones were sold worldwide, representing an astonishing 50% increase over the previous year. Maintaining such a remarkable growth rate requires constant innovation to decrease cost while increasing performance and functionality. Traditionally, wireless products have depended on a mixture of semicond- tor technologies, spanning GaAs, bipolar and BiCMOS, just to name a few. A question that has been hotly debated is whether CMOS could ever be suitable for RF applications. However, given the acknowledged inferiority of CMOS transistors relative to those in other candidate technologies, it has been argued by many that “CMOS RF” is an oxymoron, an endeavor best left cloistered in the ivory towers of academia. In rebuttal, there are several compelling reasons to consider CMOS for wi- less applications. Aside from the exponential device and density improvements delivered regularly by Moore’s law, only CMOS offers a technology path for integrating RF and digital elements, potentially leading to exceptionally c- pact and low-cost devices. To enable this achievement, several thorny issues need to be resolved. Among these are the problem of poor passive com- nents, broadband noise in MOSFETs, and phase noise in oscillators made with CMOS. Beyond the component level, there is also the important question of whether there are different architectural choices that one would make if CMOS were used, given the different constraints.




Ultra-Low Power Wireless Technologies for Sensor Networks


Book Description

This book is written for academic and professional researchers designing communication systems for pervasive and low power applications. There is an introduction to wireless sensor networks, but the main emphasis of the book is on design techniques for low power, highly integrated transceivers. Instead of presenting a single design perspective, this book presents the design philosophies from three diverse research groups, providing three completely different strategies for achieving similar goals. By presenting diverse perspectives, this book prepares the reader for the countless design decisions they will be making in their own designs.




Ultra-Low-Power Short-Range Radios


Book Description

This book explores the design of ultra-low-power radio-frequency integrated circuits (RFICs), with communication distances ranging from a few centimeters to a few meters. The authors describe leading-edge techniques to achieve ultra-low-power communication over short-range links. Many different applications are covered, ranging from body-area networks to transcutaneous implant communications and smart-appliance sensor networks. Various design techniques are explained to facilitate each of these applications.




The Design and Implementation of Low-Power CMOS Radio Receivers


Book Description

The primary goal of The Design and Implementation of Low-Power CMOS Radio Receivers is to explore techniques for implementing wireless receivers in an inexpensive complementary metal-oxide-semiconductor (CMOS) technology. Although the techniques developed apply somewhat generally across many classes of receivers, the specific focus of this work is on the Global Positioning System (GPS). Because GPS provides a convenient vehicle for examining CMOS receivers, a brief overview of the GPS system and its implications for consumer electronics is presented. The GPS system comprises 24 satellites in low earth orbit that continuously broadcast their position and local time. Through satellite range measurements, a receiver can determine its absolute position and time to within about 100m anywhere on Earth, as long as four satellites are within view. The deployment of this satellite network was completed in 1994 and, as a result, consumer markets for GPS navigation capabilities are beginning to blossom. Examples include automotive or maritime navigation, intelligent hand-off algorithms in cellular telephony, and cellular emergency services, to name a few. Of particular interest in the context of this book are embedded GPS applications where a GPS receiver is just one component of a larger system. Widespread proliferation of embedded GPS capability will require receivers that are compact, cheap and low-power. The Design and Implementation of Low-Power CMOS Radio Receivers will be of interest to professional radio engineers, circuit designers, professors and students engaged in integrated radio research and other researchers who work in the radio field.