Die-stacking Architecture


Book Description

The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the "memory wall" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to designing future 3D microprocessor systems, by leveraging the benefits of low latency, high bandwidth, and heterogeneous integration capability which are offered by 3D technology.




Die-stacking Architecture


Book Description

The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the "memory wall" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to designing future 3D microprocessor systems, by leveraging the benefits of low latency, high bandwidth, and heterogeneous integration capability which are offered by 3D technology.




Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs


Book Description

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.




Progress in VLSI Design and Test


Book Description

This book constitutes the refereed proceedings of the 16th International Symposium on VSLI Design and Test, VDAT 2012, held in Shibpur, India, in July 2012. The 30 revised regular papers presented together with 10 short papers and 13 poster sessions were carefully selected from 135 submissions. The papers are organized in topical sections on VLSI design, design and modeling of digital circuits and systems, testing and verification, design for testability, testing memories and regular logic arrays, embedded systems: hardware/software co-design and verification, emerging technology: nanoscale computing and nanotechnology.




Three-Dimensional Design Methodologies for Tree-based FPGA Architecture


Book Description

This book focuses on the development of 3D design and implementation methodologies for Tree-based FPGA architecture. It also stresses the needs for new and augmented 3D CAD tools to support designs such as, the design for 3D, to manufacture high performance 3D integrated circuits and reconfigurable FPGA-based systems. This book was written as a text that covers the foundations of 3D integrated system design and FPGA architecture design. It was written for the use in an elective or core course at the graduate level in field of Electrical Engineering, Computer Engineering and Doctoral Research programs. No previous background on 3D integration is required, nevertheless fundamental understanding of 2D CMOS VLSI design is required. It is assumed that reader has taken the core curriculum in Electrical Engineering or Computer Engineering, with courses like CMOS VLSI design, Digital System Design and Microelectronics Circuits being the most important. It is accessible for self-study by both senior students and professionals alike.




More than Moore Technologies for Next Generation Computer Design


Book Description

This book provides a comprehensive overview of key technologies being used to address challenges raised by continued device scaling and the extending gap between memory and central processing unit performance. Authors discuss in detail what are known commonly as “More than Moore” (MtM), technologies, which add value to devices by incorporating functionalities that do not necessarily scale according to “Moore's Law”. Coverage focuses on three key technologies needed for efficient power management and cost per performance: novel memories, 3D integration and photonic on-chip interconnect.




Encyclopedia Of Thermal Packaging, Set 2: Thermal Packaging Tools (A 4-volume Set)


Book Description

remove This Encyclopedia comes in 3 sets. To check out Set 1 and Set 3, please visit Set 1: Thermal Packaging Techniques and Set 3: Thermal Packaging Applications /remove Thermal and mechanical packaging - the enabling technologies for the physical implementation of electronic systems - are responsible for much of the progress in miniaturization, reliability, and functional density achieved by electronic, microelectronic, and nanoelectronic products during the past 50 years. The inherent inefficiency of electronic devices and their sensitivity to heat have placed thermal packaging on the critical path of nearly every product development effort in traditional, as well as emerging, electronic product categories.Successful thermal packaging is the key differentiator in electronic products, as diverse as supercomputers and cell phones, and continues to be of pivotal importance in the refinement of traditional products and in the development of products for new applications. The Encyclopedia of Thermal Packaging, compiled in four multi-volume sets (Set 1: Thermal Packaging Techniques, Set 2: Thermal Packaging Tools, Set 3: Thermal Packaging Applications, and Set 4: Thermal Packaging Configurations) will provide a comprehensive, one-stop treatment of the techniques, tools, applications, and configurations of electronic thermal packaging. Each of the author-written sets presents the accumulated wisdom and shared perspectives of a few luminaries in the thermal management of electronics.Set 2: Thermal Packaging ToolsThe second set in the encyclopedia, Thermal Packaging Tools, includes volumes dedicated to thermal design of data centers, techniques and models for the design and optimization of heat sinks, the development and use of reduced-order “compact” thermal models of electronic components, a database of critical material thermal properties, and a comprehensive exploration of thermally-informed electronic design. The numerical and analytical techniques described in these volumes are among the primary tools used by thermal packaging practitioners and researchers to accelerate product and system development and achieve “correct by design” thermal packaging solutions.The four sets in the Encyclopedia of Thermal Packaging will provide the novice and student with a complete reference for a quick ascent on the thermal packaging ';learning curve,'; the practitioner with a validated set of techniques and tools to face every challenge, and researchers with a clear definition of the state-of-the-art and emerging needs to guide their future efforts. This encyclopedia will, thus, be of great interest to packaging engineers, electronic product development engineers, and product managers, as well as to researchers in thermal management of electronic and photonic components and systems, and most beneficial to undergraduate and graduate students studying mechanical, electrical, and electronic engineering.




Handbook of 3D Integration, Volume 4


Book Description

This fourth volume of the landmark handbook focuses on the design, testing, and thermal management of 3D-integrated circuits, both from a technological and materials science perspective. Edited and authored by key contributors from top research institutions and high-tech companies, the first part of the book provides an overview of the latest developments in 3D chip design, including challenges and opportunities. The second part focuses on the test methods used to assess the quality and reliability of the 3D-integrated circuits, while the third and final part deals with thermal management and advanced cooling technologies and their integration.




Cooling Of Microelectronic And Nanoelectronic Equipment: Advances And Emerging Research


Book Description

To celebrate Professor Avi Bar-Cohen's 65th birthday, this unique volume is a collection of recent advances and emerging research from various luminaries and experts in the field. Cutting-edge technologies and research related to thermal management and thermal packaging of micro- and nanoelectronics are covered, including enhanced heat transfer, heat sinks, liquid cooling, phase change materials, synthetic jets, computational heat transfer, electronics reliability, 3D packaging, thermoelectrics, data centers, and solid state lighting.This book can be used by researchers and practitioners of thermal engineering to gain insight into next generation thermal packaging solutions. It is an excellent reference text for graduate-level courses in heat transfer and electronics packaging.




More-than-Moore 2.5D and 3D SiP Integration


Book Description

This book presents a realistic and a holistic review of the microelectronic and semiconductor technology options in the post Moore’s Law regime. Technical tradeoffs, from architecture down to manufacturing processes, associated with the 2.5D and 3D integration technologies, as well as the business and product management considerations encountered when faced by disruptive technology options, are presented. Coverage includes a discussion of Integrated Device Manufacturer (IDM) vs Fabless, vs Foundry, and Outsourced Assembly and Test (OSAT) barriers to implementation of disruptive technology options. This book is a must-read for any IC product team that is considering getting off the Moore’s Law track, and leveraging some of the More-than-Moore technology options for their next microelectronic product.