Digital Logic Design Based on Negative Capacitance Field Effect Transistors


Book Description

This thesis explores the circuit implications of ferroelectric transistors with a focus on the effects of ferroelectric material thickness. Ferroelectric transistors have a thin layer of ferroelectric material deposited on the gate of the device. This material causes the behavior of the device to change due to its negative capacitance. While there are many variables which contribute to this effect, with all other variables fixed, the material thickness can be used to explore some of the actions of the ferroelectric transistors.This thesis shows transistor characteristics of the ferroelectric transistors mapped with respect to the ferroelectric material thickness. A ring oscillator is also used to explore the energy and delay of the ferroelectric transistors. Also, 6T SRAM cells are explored with respect to ferroelectric transistors to understand the implications of their use within SRAM cells. Ferroelectric transistors are found to be useful in low power systems to mitigate some of the issues that traditional MOSFETs encounter when in the same setting.




Negative Capacitance Field Effect Transistors


Book Description

This book aims to provide information in the ever-growing field of low-power electronic devices and their applications in portable devices, wireless communication, sensor, and circuit domains. Negative Capacitance Field Effect Transistors: Physics, Design, Modeling and Applications discusses low-power semiconductor technology and addresses state-of-the-art techniques such as negative capacitance field effect transistors and tunnel field effect transistors. The book is split into three parts. The first part discusses the foundations of low-power electronics, including the challenges and demands and concepts such as subthreshold swing. The second part discusses the basic operations of negative capacitance field effect transistors (NCFETs) and tunnel field effect transistors (TFETs). The third part covers industrial applications including cryogenics and biosensors with NC-FET. This book is designed to be a one-stop guide for students and academic researchers, to understand recent trends in the IT industry and semiconductor industry. It will also be of interest to researchers in the field of nanodevices such as NC-FET, FinFET, tunnel FET, and device–circuit codesign.




Negative Capacitance Field Effect Transistors


Book Description

This book aims to provide information in the ever-growing field of low-power electronic devices and their applications in portable device, wireless communication, sensor, and circuit domains. . Negative Capacitance Field Effect Transistor: Physics, Design, Modeling and Applications, discusses low-power semiconductor technology and addresses state-of-art techniques such as negative-capacitance field-effect transistors and tunnel field-effect transistors. The book is broken up into four parts. Part one discusses foundations of low-power electronics including the challenges and demands and concepts like subthreshold swing. Part two discusses the basic operations of negative-capacitance field-effect transistor (NC-FET) and Tunnel Field-effect Transistor (TFET). Part three covers industrial applications including cryogenics and biosensors with NC-FET. This book is designed to be one-stop guidebook for students and academic researchers, to understand recent trends in the IT industry and semiconductor industry. It will also be of interest to researchers in the field of nanodevices like NC-FET, FinFET, Tunnel FET, and device-circuit codesign.




Development and Investigation of Novel Logic-in-Memory and Nonvolatile Logic Circuits Utilizing Hafnium Oxide-Based Ferroelectric Field-Effect Transistors


Book Description

Not only conventional computer architectures, such as the von-Neumann architecture with its inevitable von-Neumann bottleneck, but likewise the emerging field of edge computing require to substantially decrease the spatial separation of logic and memory units to overcome power and latency shortages. The integration of logic operations into memory units (Logic-in-Memory), as well as memory elements into logic circuits (Nonvolatile Logic), promises to fulfill this request by combining high-speed with low-power operation. Ferroelectric field-effect transistors (FeFETs) based on hafnium oxide prove to be auspicious candidates for the memory elements in applications of that kind, as those nonvolatile memory elements are CMOS-compatible and likewise scalable. This work presents implementations that merge logic and memory by exploiting the natural capability of the FeFET to combine logic functionality (transistor) and memory ability (nonvolatility).







Digital Logic Design Using Carbon Nanotube Field Effect Transistors


Book Description

This book presents the design of digital logic circuits using carbon nanotube field effect transistors (CNTFET). CNTFET is a promising device in the nanometer regime which utilizes a semiconducting carbon nanotube (CNT) channel between the source and drain terminals. Due to the excellent electrical properties of CNT it can offer very high speed integrated circuits. Starting with the basics of CNT and CNTFET this book discusses the modeling of CNTFET using Verilog-AMS language. The design of the basic logic gates is presented. The designs are simulated to verify their functionality and extract the speed and power performances. The design of reconfigurable logic circuits using transmission gate based logic is also presented. A ring oscillator circuit has been designed using CNTFET and it is found that the circuit can operate at very high frequency of 114 GHz.







The Applicability of Ferroelectrics for Analog and Digital Transistor Applications


Book Description

As transistors scale to ever smaller dimensions, power density becomes an increasingly important issue in integrated circuit (IC) design. Recently, negative capacitance field-effect transistors (NCFETs), realized by stacking ferroelectric material on top of conventional gate oxides, have been proposed to reduce power consumption in modern aggressively scaled devices. The negative capacitance of these ferroelectric materials provide voltage amplification to the transistor in order to reduce the subthreshold swing (SS), which would reduce the active power consumption of the device via a reduction of the supply voltage. Beyond reduction of power consumption for individual transistors, the unique negative capacitance behavior in these ferroelectric materials also offers a vast array of options in modern IC design. As a result, ferroelectric materials are an exciting area of research. The current state-of-the-art modeling approach for the dynamics of ferroelectric materials is via the Landau-Khalatnikov (LK) equation. In this work, we implement a multi-domain improvement upon the LK equation and combine it with Cadence circuit simulations to model and predict the characteristics of NCFETs and other ferroelectric devices. In the first stage of this work, we calibrate our multi-domain LK model to experimental results to show a very strong match. Using this calibrated model, we examine the potential speed limitations of NCFETs and identify the requirement on the viscosity parameter of the ferroelectric materials to provide sub-picosecond rise time required for modern transistors. In the second stage, we propose a new measurement technique for extracting the LK parameters of a ferroelectric material. We demonstrate via Cadence circuit simulation that this new measurement technique is able to accurately extract all LK parameters, including the viscosity parameter, which is difficult to extract using standard techniques. In the third stage, we propose a new application for ferroelectric materials to increase the unity-current-gain frequency ?? of a transistor. By placing the ferroelectric in parallel with the FET gate, the negative capacitance of the ferroelectric cancels the positive gate capacitance of the FET, which in turn increases the ?? . This new application offerroelectrics opens new possibilities for IC design. Overall, this work improves the understanding of ferroelectric materials pertaining to their applications in IC design, providing critical information for the electron device community as it continues to explore methods to advance the performance of nanoscale electronics into the 2030s and beyond, the current horizon of the International Roadmap for Devices and Systems.




Negative Capacitance for Ultra-low Power Computing


Book Description

Owing to the fundamental physics of the Boltzmann distribution, the ever-increasing power dissipation in nanoscale transistors threatens an end to the almost-four-decade-old cadence of continued performance improvement in complementary metal-oxide-semiconductor (CMOS) technology. It is now agreed that the introduction of new physics into the operation of field-effect transistors--in other words, ``reinventing the transistor''-- is required to avert such a bottleneck. In this dissertation, we present the experimental demonstration of a novel physical phenomenon, called the negative capacitance effect in ferroelectric oxides, which could dramatically reduce power dissipation in nanoscale transistors. It was theoretically proposed in 2008 that by introducing a ferroelectric negative capacitance material into the gate oxide of a metal-oxide-semiconductor field-effect transistor (MOSFET), the subthreshold slope could be reduced below the fundamental Boltzmann limit of 60 mV/dec, which, in turn, could arbitrarily lower the power supply voltage and the power dissipation. The research presented in this dissertation establishes the theoretical concept of ferroelectric negative capacitance as an experimentally verified fact. \\ The main results presented in this dissertation are threefold. To start, we present the first direct measurement of negative capacitance in isolated, single crystalline, epitaxially grown thin film capacitors of ferroelectric Pb(Zr$_{0.2}$Ti$_{0.8}$)O$_3$. By constructing a simple resistor-ferroelectric capacitor series circuit, we show that, during ferroelectric switching, the ferroelectric voltage decreases, while the stored charge in it increases, which directly shows a negative slope in the charge-voltage characteristics of a ferroelectric capacitor. Such a situation is completely opposite to what would be observed in a regular resistor-positive capacitor series circuit. This measurement could serve as a canonical test for negative capacitance in any novel material system. Secondly, in epitaxially grown ferroelectric Pb(Zr$_{0.2}$Ti$_{0.8}$)O$_3$-dielectric SrTiO$_3$ heterostructure capacitors, we show that negative capacitance effect from the ferroelectric Pb(Zr$_{0.2}$Ti$_{0.8}$)O$_3$ layer could result in an enhancement of the capacitance of bilayer heterostructure over that of the constituent dielectric SrTiO$_3$ layer. This observation apparently violates the fundamental law of circuit theory which states that the equivalent capacitance of two capacitors connected in series is smaller than that of each of the constituent capacitors. Finally, we present a design framework for negative capacitance field-effect-transistors and project performance for such devices.




Analysis and Design of Integrated Electronic Circuits


Book Description

This is the second edition of an undergraduate textbook that covers the core topics in electronics that all electrical engineers should know. The book has been upgraded to reflect changes in technology and in electrical engineering curricula.