Energy-aware Network Coding Circuit and System Design


Book Description

Network Coding (NC) has been shown to provide several advantages in communication networks in terms of throughput, data robustness and security. However, its applicability to networks with resource constrained nodes, like Body Area Networks (BANs), has been questioned due to its complexity requirements. Proposed NC implementations are based on high-end CPUs and GPUs, consuming hundreds of Watts, without providing enough insight about its energy requirements. As more and more mobile devices, sensors and other low power systems are used in modern communication protocols, a highly efficient and optimized implementation of NC is required. In this work, an effort is made to bridge NC theory with ultra low power applications. For this reason, an energy-scalable, low power accelerator is designed in order to explore the minimum energy requirements of NC. Based on post-layout simulation results using a TSMC 65nm process, the proposed encoder consumes 22.15 uW at 0.4V, achieving a processing throughput of 80 MB/s. These numbers reveal that NC can indeed be incorporated into resource constrained networks with battery-operated or even energy scavenging nodes. Apart from the hardware design, a new partial packet recovery mechanism based on NC, called PPRNC, is proposed. PPRNC exploits information contained in partial packets, similarly to existing Hybrid-ARQ schemes, but with a PHY-agnostic approach. Minimization of the number of retransmitted packets saves transmission energy and results in higher total network throughput, making PPRNC an attractive candidate for energy constrained networks, such as BANs, as well as modern, high-speed wireless mesh networks. The proposed mechanism is analyzed and implemented using commercial development boards, validating its ability to extract information contained from partial packets.




Energy Aware Network Coding in Wireless Networks


Book Description

Energy is one of the most important considerations in designing reliable low-power wireless communication networks. We focus on the problem of energy aware network coding. In particular, we investigate practical energy efficient network code design for wireless body area networks (WBAN). We first consider converge-cast in a star-shaped topology, in which a central base station (BS), or hub, manages and communicates directly with a set of nodes. We then consider a wireless-relay channel, in which a relay node assists in the transmission of data from a source to a destination. This wireless relay channel can be seen as a simplified extended star network, where nodes have relay capabilities. The objective is to investigate the use of network coding in these scenarios, with the goal of achieving reliability under low-energy and lower-power constraints. More specifically, in a star network, we propose a simple network layer protocol, study the mean energy to complete uploads of given packets from the nodes to the BS using a Markov chain model, and show through numerical examples that when reception energy is taken into account, the incorporation of network coding offers reductions in energy use. The amount of achievable gains depends on the number of nodes in the network, the degree of asymmetry in channel conditions experienced by different nodes, and the relative difference between transmitting and receiving power at the nodes. We also demonstrate the compatibility of the proposed scheme with the IEEE 802.15.6 WBAN standard by describing ways of incorporating network coding into systems compliant to the standard. For a wireless relay channel, we explore the strategic use of network coding according to both throughput and energy metrics. In the relay channel, a single source communicates to a single sink through the aid of a half-duplex relay. The fluid flow model is used to describe the case where both the source and the relay are coding, and Markov chain models are proposed to describe packet evolution if only the source or only the relay is coding. Although we do not attempt to explicitly categorize the optimal network coding strategies in the relay channel under different system parameters, we provide a framework for deciding whether and where to code, taking into account of throughput maximization and energy depletion constraints.




Energy-Aware Systems and Networking for Sustainable Initiatives


Book Description

"This book covers a great variety of topics such as materials, environment, electronics, and computing, offering a vital source of information detailing the latest architectures, frameworks, methodologies, and research on energy-aware systems and networking for sustainable initiatives"--




Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation


Book Description

This volume features the refereed proceedings of the 17th International Workshop on Power and Timing Modeling, Optimization and Simulation. Papers cover high level design, low power design techniques, low power analog circuits, statistical static timing analysis, power modeling and optimization, low power routing optimization, security and asynchronous design, low power applications, modeling and optimization, and more.




Power Aware Design Methodologies


Book Description

Power Aware Design Methodologies was conceived as an effort to bring all aspects of power-aware design methodologies together in a single document. It covers several layers of the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. It includes discussion of techniques and methodologies for improving the power efficiency of CMOS circuits (digital and analog), systems on chip, microelectronic systems, wirelessly networked systems of computational nodes and so on. In addition to providing an in-depth analysis of the sources of power dissipation in VLSI circuits and systems and the technology and design trends, this book provides a myriad of state-of-the-art approaches to power optimization and control. The different chapters of Power Aware Design Methodologies have been written by leading researchers and experts in their respective areas. Contributions are from both academia and industry. The contributors have reported the various technologies, methodologies, and techniques in such a way that they are understandable and useful.




Low Power Networks-on-Chip


Book Description

In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.




Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation


Book Description

This book constitutes the refereed proceedings of the 15th International Workshop on Power and Timing Optimization and Simulation, PATMOS 2005, held in Leuven, Belgium in September 2005. The 74 revised full papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-power processors, code optimization for low-power, high-level design, telecommunications and signal processing, low-power circuits, system-on-chip design, busses and interconnections, modeling, design automation, low-power techniques, memory and register files, applications, digital circuits, and analog and physical design.




Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation


Book Description

This book constitutes the refereed proceedings of the 20th International Conference on Integrated Circuit and System Design, PATMOS 2010, held in Grenoble, France, in September 2010. The 24 revised full papers presented and the 9 extended abstracts were carefully reviewed and are organized in topical sections on design flows; circuit techniques; low power circuits; self-timed circuits; process variation; high-level modeling of poweraware heterogeneous designs in SystemC-AMS; and minalogic.




Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation


Book Description

This book constitutes the refereed proceedings of the 21st International Conference on Integrated Circuit and System Design, PATMOS 2011, held in Madrid, Spain, in September 2011. The 34 revised full papers presented were carefully reviewed and selected from numerous submissions. The paper feature emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems and focus especially on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization.




Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation


Book Description

This book constitutes the refereed proceedings of the 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2003, held in Torino, Italy in September 2003. The 43 revised full papers and 18 revised poster papers presented together with three keynote contributions were carefully reviewed and selected from 85 submissions. The papers are organized in topical sections on gate-level modeling and characterization, interconnect modeling and optimization, asynchronous techniques, RTL power modeling and memory optimization, high-level modeling, power-efficient technologies and designs, communication modeling and design, and low-power issues in processors and multimedia.