Author : Taemin Kim
Publisher :
Page : 105 pages
File Size : 14,93 MB
Release : 2009
Category :
ISBN :
Keywords: high level synthesis, global interconnect, VLSI CAD, optimization, algorithm.
Author :
Publisher :
Page : pages
File Size : 13,85 MB
Release : 2004
Category :
ISBN :
Optimization techniques during high level synthesis procedure are often preferred since design decisions at early stages of a design à ̄¬‚ow are believed to have a large impact on design quality. In this dissertation, we present three high-level synthesis schemes to improve the power, speed and reliability of deep submicron VLSI systems. Specià ̄¬ cally, we à ̄¬ rst describe a simultaneous register and functional unit (FU) binding algorithm. Our algorithm targets the reduction of multiplexer inputs, shortening the total length of global interconnects. In this algorithm, we introduce three graph parameters that guide our FU and register binding. They are à ̄¬‚ow dependencies, common primary inputs and common register inputs. We maximize the interconnect sharing among FUs and registers. We then present an interconnect binding algorithm during high-level synthesis for global intercon- nect reduction. Our scheme is based on the observation that not all FUs operate at all time. When idle, FUs can be reconà ̄¬ gured as pass-through logic for data transfer, reducing interconnect requirement. Our scheme not only reduces the overall length of global interconnects but also minimizes the power overhead without introducing any timing violations. Lastly, we present a register binding algorithm with the ob jective of register minimization. We have observed that not all pipelined FUs are operating at all time. Idle pipelined FUs can be used to store data temporarily, reducing stand-alone registers.
Author : Philippe Coussy
Publisher : Springer Science & Business Media
Page : 307 pages
File Size : 38,90 MB
Release : 2008-08-01
Category : Technology & Engineering
ISBN : 1402085885
This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. It includes an overview of available EDA tool solutions and their applicability to design problems.
Author : Raul Camposano
Publisher : Springer Science & Business Media
Page : 395 pages
File Size : 47,42 MB
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 1461539668
The time has come for high-level synthesis. When research into synthesizing hardware from abstract, program-like de scriptions started in the early 1970' s, there was no automated path from the register transfer design produced by high-level synthesis to a complete hardware imple mentation. As a result, it was very difficult to measure the effectiveness of high level synthesis methods; it was also hard to justify to users the need to automate architecture design when low-level design had to be completed manually. Today's more mature CAD techniques help close the gap between an automat ically synthesized design and a manufacturable design. Market pressures encour age designers to make use of any and all automated tools. Layout synthesis, logic synthesis, and specialized datapath generators make it feasible to quickly imple ment a register-transfer design in silicon,leaving designers more time to consider architectural improvements. As IC design becomes more automated, customers are increasing their demands; today's leading edge designers using logic synthesis systems are training themselves to be tomorrow's consumers of high-level synthe sis systems. The need for very fast turnaround, a competitive fabrication market WhlCh makes small-quantity ASIC manufacturing possible, and the ever growing co:n plexity of the systems being designed, all make higher-level design automaton inevitable.
Author : Michael Fingeroff
Publisher : Xlibris Corporation
Page : 334 pages
File Size : 42,5 MB
Release : 2010
Category : Computers
ISBN : 1450097243
Are you an RTL or system designer that is currently using, moving, or planning to move to an HLS design environment? Finally, a comprehensive guide for designing hardware using C++ is here. Michael Fingeroff's High-Level Synthesis Blue Book presents the most effective C++ synthesis coding style for achieving high quality RTL. Master a totally new design methodology for coding increasingly complex designs! This book provides a step-by-step approach to using C++ as a hardware design language, including an introduction to the basics of HLS using concepts familiar to RTL designers. Each chapter provides easy-to-understand C++ examples, along with hardware and timing diagrams where appropriate. The book progresses from simple concepts such as sequential logic design to more complicated topics such as memory architecture and hierarchical sub-system design. Later chapters bring together many of the earlier HLS design concepts through their application in simplified design examples. These examples illustrate the fundamental principles behind C++ hardware design, which will translate to much larger designs. Although this book focuses primarily on C and C++ to present the basics of C++ synthesis, all of the concepts are equally applicable to SystemC when describing the core algorithmic part of a design. On completion of this book, readers should be well on their way to becoming experts in high-level synthesis.
Author : Zi Wang
Publisher :
Page : 0 pages
File Size : 12,20 MB
Release : 2021
Category : Space sciences
ISBN :
To address the increase in Very Large-Scale Integration (VLSI) design complexity, companies have started to embrace High-Level Synthesis (HLS) as an alternative to traditional Register Transfer Level (RTL) VLSI design based on low-level hardware description languages (HDLs) such as Verilog or VHDL. HLS takes high level languages, such as ANSI-C, C++ or SystemC, as input and generate efficient RTL code. One of the most salient advantages of HLS is that it allows users to generate different designs by simply changing the synthesis options. Setting different combinations of these options lead to micro-architectures with different area, latency, power trade-offs. Among all the possible micro-architectures, the designer is typically only concerned about the Pareto-optimal ones. However, due to the exponential growth of the synthesis options search space, exhaustive enumerations are not possible. Thus, most work in the HLS Design Space Exploration (DSE) domain deals with the design of efficient heuristics. The main research contribution in this dissertation has been to investigate efficient HLS DSE methods. Firstly we analyse the relationship between meta-heuristics0́9 hyper parameters and their performance. Secondly, we introduce a new method based on transfer learning. This implies that the results from previous HLS DSE results are leveraged to more efficiently explore the search space of a new, unseen behavioral description. On the other hand, raising the level of abstraction opens the door to a new service model based on Behavioral IPs (BIPs). Unfortunately not many particular methods exist to protect the BIP providers from their BIPs being illegally distribute. In this dissertation I investigate a new business model that allows to lock the search space of BIPs by partially encrypting it. This has the benefit of allowing a new price discrimination policy. BIP consumers that want a fully visible BIP would need to pay more, while BIPs what only want a partially explorable BIP are expected to pay less. Finally, this dissertation investigates the use of embedded Field Programmable Gate Arrays (eFPGAs) in the context of BIP logic locking by judiciously extracting a portion of a BIP for HLS onto an eFPGA while mapping the rest on an Application Specific Integrated Circuit (ASIC).
Author : Minjoong Rim
Publisher :
Page : 444 pages
File Size : 20,41 MB
Release : 1993
Category :
ISBN :
Author : Daniel D. Gajski
Publisher : Springer Science & Business Media
Page : 368 pages
File Size : 50,89 MB
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 1461536367
Research on high-level synthesis started over twenty years ago, but lower-level tools were not available to seriously support the insertion of high-level synthesis into the mainstream design methodology. Since then, substantial progress has been made in formulating and understanding the basic concepts in high-level synthesis. Although many open problems remain, high-level synthesis has matured. High-Level Synthesis: Introduction to Chip and System Design presents a summary of the basic concepts and results and defines the remaining open problems. This is the first textbook on high-level synthesis and includes the basic concepts, the main algorithms used in high-level synthesis and a discussion of the requirements and essential issues for high-level synthesis systems and environments. A reference text like this will allow the high-level synthesis community to grow and prosper in the future.
Author : Filip Thoen
Publisher : Springer Science & Business Media
Page : 446 pages
File Size : 31,8 MB
Release : 2012-12-06
Category : Computers
ISBN : 1461544378
system is a complex object containing a significant percentage of elec A tronics that interacts with the Real World (physical environments, humans, etc. ) through sensing and actuating devices. A system is heterogeneous, i. e. , is characterized by the co-existence of a large number of components of disparate type and function (for example, programmable components such as micro processors and Digital Signal Processors (DSPs), analog components such as AID and D/A converters, sensors, transmitters and receivers). Any approach to system design today must include software concerns to be viable. In fact, it is now common knowledge that more than 70% of the development cost for complex systems such as automotive electronics and communication systems are due to software development. In addition, this percentage is increasing constantly. It has been my take for years that the so-called hardware-software co-design problem is formulated at a too low level to yield significant results in shorten ing design time to the point needed for next generation electronic devices and systems. The level of abstraction has to be raised to the Architecture-Function co-design problem, where Function refers to the operations that the system is supposed to carry out and Architecture is the set of supporting components for that functionality. The supporting components as we said above are heteroge neous and contain almost always programmable components.
Author : Gabriele Saucier
Publisher : Springer
Page : 381 pages
File Size : 26,8 MB
Release : 2016-01-09
Category : Technology & Engineering
ISBN : 0387349200
This book describes several methods and systems solving one of the highlighted problems within computer aided design, namely architectural and logic synthesis. The book emphasises the most recent technologies in high level synthesis, concentrating on applicative studies and practical constraints or criteria during synthesis. Logic and Architecture Synthesis concentrates on the practical problems involving automatic synthesis of designs. It is essential reading for researchers and CAD Managers working in this area.
