Book Description

In the emerging applications of the Internet of Things (IoT) -- the vision of ubiquitous and pervasive sensing, collecting, and managing data through various sensors, communication technologies, and data analytic techniques, billions of sensors are attached to different objects. The power consumption of the analog front-end circuits in a sensor system is one of the most stringent requirements. The low-power consumption not only can be environment-friendly but also can benefit the customers economically. This thesis presents a suite of design on the low power interface circuits for the energy-constrained sensing applications. First, an always-on input-biased sub-nanowatt millivolt hysteretic threshold detector for near-zero energy sensing applications is introduced. The threshold detector compares two pA currents generated by current mirrors biased by the mV-range input signal. With the input signal near zero at the standby mode, the threshold detector consumes near-zero energy. Positive feedback is introduced to accelerate the output signal transition and generate the hysteresis to tolerate the noise in the input signal. Designed and fabricated in a standard 65 nm CMOS process, the proposed threshold detector achieved programmable thresholds from 27 to 46.5 mV with energy per switching from 1.9 to 2.4 nJ using four control bits with a 10 Hz input. While the static power consumption is 270 pW measured at the input signal of 0.1 mV with a frequency of 10 Hz. Second, a resistor-based highly-digital temperature sensor with a SAR-quantization embedded differential low-pass filter is presented for integrated SoC thermal detection. It has three unique features: (1) the use of a differential low-pass RC filter (DLPF) for thermal sensing, which reduces the area; (2) SAR-quantization embedded in the DLPF, which reuses the DLPF capacitor for capacitive digital to analog conversion (CDAC), eliminates the CDAC references, and utilizes the full sensing range for quantization; and (3) a highly-digital circuit architecture, which can be easily implemented using a standard digital design flow and migrated to different processes. The temperature sensor was fabricated in a 65nm CMOS technology occupying 8400 [micro]m2 silicon area. It achieves 0.38 °C resolution at room temperature. After a 2-point calibration, the sensor achieves a 3[sigma] inaccuracy of ±1.2 °C from -30 to 100 °C. It consumes 35.3 [micro]W power from a 1.1 V supply. With a 2.5 [micro]W conversion time, the sensor achieves an 88 pJ/Conversion energy efficiency, which yields a 12.7 pJ·K2 resolution figure-of-merit (FoM). Finally, we move on to another interface circuit, analog-to-digital converter (ADC). An energy-efficient, area-compact successive-approximation-register (SAR) ADC based on passive charge sharing is introduced. For each bit decision, a bit reference capacitor with capacitance [Beta] times larger than that of the bit weight capacitor and precharged to the reference level is introduced to replace the precise reference source. Closed-form analytic expressions of ADC transfer functions are derived based on charge conservation and validated by behavioral and schematic simulations. Based on the derived results, and using the bitwise passive charge sharing technique, an 11-bit segmented SAR ADC that comprises a 5-bit coarse ADC and a 12-bit fine ADC has been designed and fabricated in a 65~nm CMOS technology, occupying 0.076 mm2. The fabricated ADC has been measured to achieve a peak SNDR of 60.6 dB and SFDR of 72 dB, and to dissipate 240 [micro]W under 1.2 V supply at 25 MS/s, including 70 [micro]W used by on-chip reference charge reservoir drivers, leading to a Figure of Merit (FoM) of 11.8 fJ/conversion-step at the input frequency of 2.43 MHz.