Simultaneous Switching Noise of CMOS Devices and Systems


Book Description

This monograph presents our recent research on Simultaneous Switching Noise (SSN) and related issues for CMOS based systems. Although some SSN related work was previously reported in the literature, it were mainly for Emitter Coupled Logic (ECL) gates using Bipolar Junction Transistors (BJTs). This present work covers in-depth analysis on estimating SSN and its impact for CMOS based devices and systems. At present semiconductor industries are moving towards scaled CMOS devices and reduced supply voltage. SSN together with coupled noise may limit the packing density, and thereby the frequency of operation of packaged systems. Our goal is to provide efficient and yet reliable methodologies and algorithms to estimate the overall noise containment in single chip and multi-chip package assemblies. We hope that the techniques and results described in this book will be useful as guides for design, package, and system engineers and academia working in this area. Through this monograph, we hope that we have shown the necessity of interactions that are essential between chip design, system design and package design engineers to design and manufacture optimal packaged systems. Work reported in this monograph was partially supported by the grant from Semiconductor Research Corporation (SRC Contract No. 92-MP-086).




Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs


Book Description

Modern microelectronic design is characterized by the integration of full systems on a single die. These systems often include large high performance digital circuitry, high resolution analog parts, high driving I/O, and maybe RF sections. Designers of such systems are constantly faced with the challenge to achieve compatibility in electrical characteristics of every section: some circuitry presents fast transients and large consumption spikes, whereas others require quiet environments to achieve resolutions well beyond millivolts. Coupling between those sections is usually unavoidable, since the entire system shares the same silicon substrate bulk and the same package. Understanding the way coupling is produced, and knowing methods to isolate coupled circuitry, and how to apply every method, is then mandatory knowledge for every IC designer. Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs is an in-depth look at coupling through the common silicon substrate, and noise at the power supply lines. It explains the elementary knowledge needed to understand these phenomena and presents a review of previous works and new research results. The aim is to provide an understanding of the reasons for these particular ways of coupling, review and suggest solutions to noise coupling, and provide criteria to apply noise reduction. Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs is an ideal book, both as introductory material to noise-coupling problems in mixed-signal ICs, and for more advanced designers facing this problem.




Power Distribution Networks with On-Chip Decoupling Capacitors


Book Description

This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power distribution systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this second edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.




Inside NAND Flash Memories


Book Description

Digital photography, MP3, digital video, etc. make extensive use of NAND-based Flash cards as storage media. To realize how much NAND Flash memories pervade every aspect of our life, just imagine how our recent habits would change if the NAND memories suddenly disappeared. To take a picture it would be necessary to find a film (as well as a traditional camera...), disks or even magnetic tapes would be used to record a video or to listen a song, and a cellular phone would return to be a simple mean of communication rather than a multimedia console. The development of NAND Flash memories will not be set down on the mere evolution of personal entertainment systems since a new killer application can trigger a further success: the replacement of Hard Disk Drives (HDDs) with Solid State Drives (SSDs). SSD is made up by a microcontroller and several NANDs. As NAND is the technology driver for IC circuits, Flash designers and technologists have to deal with a lot of challenges. Therefore, SSD (system) developers must understand Flash technology in order to exploit its benefits and countermeasure its weaknesses. Inside NAND Flash Memories is a comprehensive guide of the NAND world: from circuits design (analog and digital) to Flash reliability (including radiation effects), from testing issues to high-performance (DDR) interface, from error correction codes to NAND applications like Flash cards and SSDs.




Inside Solid State Drives (SSDs)


Book Description

The revised second edition of this respected text provides a state-of-the-art overview of the main topics relating to solid state drives (SSDs), covering NAND flash memories, memory controllers (including booth hardware and software), I/O interfaces (PCIe/SAS/SATA), reliability, error correction codes (BCH and LDPC), encryption, flash signal processing and hybrid storage. Updated throughout to include all recent work in the field, significant changes for the new edition include: A new chapter on flash memory errors and data recovery procedures in SSDs for reliability and lifetime improvement Updated coverage of SSD Architecture and PCI Express Interfaces moving from PCIe Gen3 to PCIe Gen4 and including a section on NVMe over fabric (NVMf) An additional section on 3D flash memories An update on standard reliability procedures for SSDs Expanded coverage of BCH for SSDs, with a specific section on detection A new section on non-binary Low-Density Parity-Check (LDPC) codes, the most recent advancement in the field A description of randomization in the protection of SSD data against attacks, particularly relevant to 3D architectures The SSD market is booming, with many industries placing a huge effort in this space, spending billions of dollars in R&D and product development. Moreover, flash manufacturers are now moving to 3D architectures, thus enabling an even higher level of storage capacity. This book takes the reader through the fundamentals and brings them up to speed with the most recent developments in the field, and is suitable for advanced students, researchers and engineers alike.




Analog Design Issues in Digital VLSI Circuits and Systems


Book Description

Analog Design Issues in Digital VLSI Circuits and Systems brings together in one place important contributions and up-to-date research results in this fast moving area. Analog Design Issues in Digital VLSI Circuits and Systems serves as an excellent reference, providing insight into some of the most challenging research issues in the field.




On-Chip Power Delivery and Management


Book Description

This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power delivery and management systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this fourth edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.




Handbook of Semiconductor Manufacturing Technology


Book Description

Retaining the comprehensive and in-depth approach that cemented the bestselling first edition's place as a standard reference in the field, the Handbook of Semiconductor Manufacturing Technology, Second Edition features new and updated material that keeps it at the vanguard of today's most dynamic and rapidly growing field. Iconic experts Robert Doering and Yoshio Nishi have again assembled a team of the world's leading specialists in every area of semiconductor manufacturing to provide the most reliable, authoritative, and industry-leading information available. Stay Current with the Latest Technologies In addition to updates to nearly every existing chapter, this edition features five entirely new contributions on... Silicon-on-insulator (SOI) materials and devices Supercritical CO2 in semiconductor cleaning Low-κ dielectrics Atomic-layer deposition Damascene copper electroplating Effects of terrestrial radiation on integrated circuits (ICs) Reflecting rapid progress in many areas, several chapters were heavily revised and updated, and in some cases, rewritten to reflect rapid advances in such areas as interconnect technologies, gate dielectrics, photomask fabrication, IC packaging, and 300 mm wafer fabrication. While no book can be up-to-the-minute with the advances in the semiconductor field, the Handbook of Semiconductor Manufacturing Technology keeps the most important data, methods, tools, and techniques close at hand.




Nanometer Technology Designs


Book Description

Traditional at-speed test methods cannot guarantee high quality test results as they face many new challenges. Supply noise effects on chip performance, high test pattern volume, small delay defect test pattern generation, high cost of test implementation and application, and utilizing low-cost testers are among these challenges. This book discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the transition fault test.




VLSI Test Principles and Architectures


Book Description

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. - Most up-to-date coverage of design for testability. - Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. - Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.